IoT 용 초저전력 터널링 트랜지스터 소자 기술

  • 박종한 (서강대학교 전자공학과) ;
  • 최우영 (서강대학교 전자공학과)
  • Published : 2016.01.25

Abstract

Keywords

References

  1. K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Buechler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. Mchlntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Schifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging", Int. Electron Devices Meeting Technical Dig., IEDM 2007, pp. 247-250, 2007.
  2. D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K Asano, C. Kuo, T. -J. K. Liu, J. B. Bokor, and C. Hu, "FinFET-a selfaligned double-gate MOSFET scalable to 20 nm", IEEE Trans. Electron Devices, vol. 47, pp. 2320-2325, 2000. https://doi.org/10.1109/16.887014
  3. K. Rim, J. L. Hoyt, and F. Gibbons "Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFETs", IEEE Trans. Electron Devices, vol. 47, pp. 1406-1415, 2000. https://doi.org/10.1109/16.848284
  4. P. Packan, "Device and Circuit Interactions," Int. Electron Devices Meeting., IEDM 2008, Short Course: Performance Boosters for Advanced CMOS Devices.
  5. W. Y. Choi, B.-G. Park, J.D. Lee and T. -J. K. Liu, "Tunneling Field-Effect Transistors (TFETs) with Subthreshold Swing (SS) Less than 60 mV/dec", IEEE Electron Deivce Lett., vol. 32, no. 4, pp.437-439, 2011. https://doi.org/10.1109/LED.2011.2106757
  6. A. M. Ionescu, H. Riel, "Tunnel Field-Effect Transistors as Energy-Efficient Electronic Switches", Nature 479 (2011), 329-337. https://doi.org/10.1038/nature10679
  7. J. Appenzeller, J Knoch, M Bjoerk, H. Riel, H. Schmid, "Toward Nanowire Electronics", IEEE Trans. Electron Devices vol. 55, pp. 2827-2845, 2008. https://doi.org/10.1109/TED.2008.2008011
  8. J. -S. Jang and W. Y. Choi, "Ambipolarity Factor of Tunneling Field-Effect Transistors (TFETs)", J.Senmicond. Technol. Sci., vol. 11, no. 4, pp 272-277, 2011 https://doi.org/10.5573/JSTS.2011.11.4.272
  9. W. Y. Choi and W. Lee, "Hetero-Gate-Dielctric Tunneling field-effect Transistors", IEEE Trans. Electron Devices, vol. 57, no. 9, pp. 2317-2319, 2010. https://doi.org/10.1109/TED.2010.2052167
  10. S. Saurabh and M. J. Kumar, "Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor", IEEE Trans. Electron Devices, vol. 58, no. 2, pp. 404-410, 2011. https://doi.org/10.1109/TED.2010.2093142
  11. A. Tura, Z. Zhang, P. Liu, Y. -H. Xie and J. C. S. Woo, "Verrical Silicon p-n-p-n Tunnel nMOSFET With MBE-Grown Tunneling Junction", IEEE Trans. Electron Devices, vol. 58, no. 7, pp. 1907-1913, 2011. https://doi.org/10.1109/TED.2011.2148118
  12. K. -H. Kao, A. S. Verhulst, W. G. Vandenberghe, B. Soree, W. Magnus, D. Leonelli, G. Groeseneken and K. D. Meyer, "Optimization of Gate-on-Source-Only Tunnel FETs With Counter-Doped Pockets", IEEE Trans. Electron Devices, vol. 59, no. 8, pp. 2070-2077, 2012. https://doi.org/10.1109/TED.2012.2200489
  13. D. Leonelli, A. Vandooren, R. Rooyackers, A. S. Verhulst, C. Huyghebaert, S. D. Gendt, M. M. Heyns and G. Groeseneken, "Novel Architecture to Boost the Vertical Tunneling in Tunnel Field Effect Transistors", in Proc. IEEE Int. SOI Conf., 2011, pp. 1-2.
  14. Y. Morita, T. Mori, S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, T. Matsukawa, K. Endo, S. I. Ouchi, Y. Liu, M. Masahara, and H. Ota, "Performance Evaluation of Parallel Electric Field Tunnel Field-Effect Transistor by a distributedelement circuit model", Solid-State Electron., vol. 102, no. 3, pp. 82-86, 2014. https://doi.org/10.1016/j.sse.2014.06.007