한국정보통신학회논문지 (Journal of the Korea Institute of Information and Communication Engineering)

  • 제20권11호
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  • Pages.2093-2099
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  • 2016
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  • 2234-4772(pISSN)
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  • 2288-4165(eISSN)
한국정보통신학회 (The Korea Institute of Information and Commucation Engineering)
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다중 블록 암호 알고리듬을 지원하는 암호 프로세서

A Crypto-processor Supporting Multiple Block Cipher Algorithms

  • Cho, Wook-Lae (School of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Kim, Ki-Bbeum (School of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Bae, Gi-Chur (School of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Shin, Kyung-Wook (School of Electronic Engineering, Kumoh National Institute of Technology)
  • 투고 : 2016.11.01
  • 심사 : 2016.11.10
  • 발행 : 2016.11.30
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초록

PRESENT, ARIA, AES의 3가지 블록 암호 알고리듬을 지원하는 다중 암호 프로세서 설계에 대해 기술한다. 설계된 암호 칩은 PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES) 그리고 AES-16b 코어로 구성된다. 64-비트 블록암호 PRESENT를 구현하는 PRmo 코어는 80-비트, 128-비트 키 길이와 ECB, CBC, OFB, CTR의 4가지 운영모드를 지원한다. 128-비트, 256-비트 키 길이를 지원하는 AR_AS 코어는 128-비트 블록암호 ARIA와 AES를 자원공유 기법을 적용하여 단일 데이터 패스로 통합 구현되었다. 128-비트 키 길이를 지원하는 AES-16b 코어는 저면적 구현을 위해 16-비트의 데이터패스로 설계되었다. 각 암호 코어는 on-the-fly 키 스케줄러를 포함하고 있으며, 평문/암호문 블록의 연속적인 암호/복호화 처리가 가능하다. FPGA 검증을 통해 설계된 다중 블록 암호 프로세서의 정상 동작을 확인하였다. $0.18{\mu}m$ 공정의 CMOS 셀 라이브러리로 합성한 결과, 54,500 GEs (gate equivalents)로 구현이 되었으며, 55 MHz의 클록 주파수로 동작 가능하다.

This paper describes a design of crypto-processor that supports multiple block cipher algorithms of PRESENT, ARIA, and AES. The crypto-processor integrates three cores that are PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES), and AES-16b. The PRmo core implementing 64-bit block cipher PRESENT supports key length 80-bit and 128-bit, and four modes of operation including ECB, CBC, OFB, and CTR. The AR_AS core supporting key length 128-bit and 256-bit integrates two 128-bit block ciphers ARIA and AES into a single data-path by utilizing resource sharing technique. The AES-16b core supporting key length 128-bit implements AES with a reduced data-path of 16-bit for minimizing hardware. Each crypto-core contains its own on-the-fly key scheduler, and consecutive blocks of plaintext/ciphertext can be processed without reloading key. The crypto-processor was verified by FPGA implementation. The crypto-processor implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,500 gate equivalents (GEs), and it can operate with 55 MHz clock frequency.

키워드

참고문헌

  1. Q. Jing, et al, "Security of the Internet of Things: perspectives and challenges," Wireless Networks, Springer, vol. 20, no. 8, pp. 2481-2501, Nov. 2014. https://doi.org/10.1007/s11276-014-0761-7
  2. FIPS-197, Advanced Encryption Standard, National Institute of Standard and Technology(NIST), Nov. 2001.
  3. KS X 1213:2004, 128 bit Block Encryption Algorithm ARIA, Korean Agency for Technology and Standards(KATS), 2004.
  4. A. Bogdanov et al., "PRESENT: An Ultra-Lightweight Block Cipher," Cryptographic Hardware and Embedded Systems (CHES 2007), LNCS, Springer, vol. 4727, pp.450-466, Aug. 2007.
  5. TTA std. TTAK.KO-12.0040/R1, 64-bit Block Cipher HIGHT, Korea Internet&Security Agency, 2008.
  6. TTA std. TTAK.KO-12.0223, 128-Bit Block Cipher LEA, Telecommunications Technology Association, 2013.
  7. Sony Corporation. The 128-bit Block Cipher CLEFIA: Algorithm Specification, [Internet]. Available: http://www.sony.net/Products/cryptography/clefia/download/data/clefia-spec-1.0.pdf.
  8. CryptoLUX. Lightweight Block Ciphers, [Internet]. Available: https://www.cryptolux.org/index.php/Lightweight_Block_Ciphers
  9. M. J. Sung and K. W. Shin, "An Efficient Hardware Implementation of Lightweight Block Cipher LEA-128/192/256 for IoT Security Applications," Journal of KIICE, vol. 19, no. 7, pp. 1608-1616, Jul. 2015.
  10. G. C. Bae and K. W. Shin, "An Efficient Hardware Implementation of Lightweight Block Cipher Alforithm CLEFIA for IoT Security Applications," Journal of KIICE, vol. 20, no. 2, pp. 351-358, Feb. 2016.
  11. K. B. Kim, W. L. Cho and K.W. Shin "A Design of PRESENT Crypto-Processor Supporting ECB/CBC/OFB/CTR Modes of Operation and Key Lengths of 80/128-bit," Journal of KIICE, vol. 20, no.6, pp. 1163-1170, Jun. 2016.