Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
권호 표지
DOI QR코드

DOI QR Code

A 10-bit 10-MS/s SAR ADC with a Reference Driver

Reference Driver를 사용한 10비트 10MS/s 축차근사형 아날로그-디지털 변환기

  • Son, Jisu (Department of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Lee, Han-Yeol (Department of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Kim, Yeong-Woong (Department of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Jang, Young-Chan (Department of Electronic Engineering, Kumoh National Institute of Technology)
  • Received : 2016.07.07
  • Accepted : 2016.08.02
  • Published : 2016.12.31
Download PDF
⟨ Previous Next ⟩

Abstract

This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) with a reference driver. The proposed SAR ADC consists of a capacitive digital-to-analog converter (CDAC), a comparator, a SAR logic, and a reference driver which improves the immunity to the power supply noise. The reference driver generates the reference voltages of 0.45 V and 1.35 V for the SAR ADC with an input voltage range of ${\pm}0.9V$. The SAR ADC is implemented using a $0.18-{\mu}m$ CMOS technology with a 1.8-V supply. The proposed SAR ADC including the reference driver almost maintains an input voltage range to be ${\pm}0.9V$ although the variation of supply voltage is +/- 200 mV. It consumes 5.32 mW at a sampling rate of 10 MS/s. The measured ENOB, DNL, and INL of the ADC are 9.11 bit, +0.60/-0.74 LSB, and +0.69/-0.65 LSB, respectively.

본 논문은 reference driver를 이용한 10비트 10MS/s 축차근사형(SAR: Successive Approximation Register) 아날로그-디지털 변환기(ADC: Analog-to-Digital Converter)를 제안한다. 제안하는 SAR ADC는 커패시터형 디지털-아날로그 변환기(CDAC: Capacitive Digital-to-Analog Converter), 비교기, SAR 로직, 그리고 공급 전압 노이즈에 대한 내성을 향상시키는 reference driver로 구성된다. ${\pm}0.9V$의 아날로그 입력전압을 가지는 SAR ADC를 위해 reference driver는 0.45V, 1.35V의 기준 전압을 생성한다. 설계된 SAR ADC는 $0.18{\mu}m$ CMOS 공정을 이용하여 제작되었으며 1.8V의 공급전압을 사용하였다. 제안된 SAR ADC는 reference driver를 이용하여 +/- 200mV의 공급 전압 변화에서도 ${\pm}0.9V$의 입력 범위를 유지한다. 10MS/s의 샘플링 주파수에서 5.32mW의 전력을 소모한다. 측정된 ENOB는 9.11 비트 이며, DNL과 INL은 각각 +0.60/-0.74 LSB와 +0.69/-0.65 LSB이다.

Keywords

References

  1. C. H. Lee, K. McClellan, and J. Choma, "Supply Noise Insensitive Bandgap Regulator Using Capacitive Charge Pump DC-DC Converter," IEEE International Symposium on Circuits and Systems, vol. 6, pp. 89-92, June 1999.
  2. I. A. Young, J. K. Greason and K. L. Wong, "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors," IEEE Journal of Solid-State Circuits, vol. 27, no. 11, pp. 1599-1607, Nov. 1992. https://doi.org/10.1109/4.165341
  3. P. Harikumar and J. J. Wikner, "Design of a Reference Voltage Buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS," IEEE International Symposium on Circuits and Systems, pp. 249-252, May 2015.
  4. F. Borghetti, et al., "A programmable 10b up-to-6MS/s SAR-ADC featuring constant-FoM with on-chip reference voltage buffers," in Proc. European Solid-State Circuits Conference, pp. 500-503, Sep. 2006.
  5. S. M. Park, et al., "A 10-bit 20-MS/s Asynchronous SAR ADC with Controllable Analog Input Voltage Range and Meta-stability Detection Circuit," IEEE International SoC Design Conference, pp. 202-203, Nov. 2014.
  6. Y. Zhu, et al., "A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS," IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, June 2010. https://doi.org/10.1109/JSSC.2010.2048498
  7. G. A. Rincon Mora and P. E. Allen, "A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator," IEEE Journal of Solid-State Circuits, vol. 33, no. 1, pp. 36-44, Jan. 1998. https://doi.org/10.1109/4.654935
  8. J. H. Li, X. B. Zhang and M. Y. Yu, "A 166MS/s 31mW pipelined interpolating ADC in $0.18{\mu}m$ CMOS with on-chip LDO regulator," IEEE Cross Strait Quad-Regional Radio Science and Wireless Technology Conference, vol. 2, no. 1, pp. 1520-1524, July 2011.

Cited by

  1. 단일 입력 SAR ADC를 이용한 AMOLED 픽셀 문턱 전압 감지 회로 vol.24, pp.3, 2016, https://doi.org/10.7471/ikeee.2020.24.3.719