Journal of Korean Society of Industrial and Systems Engineering (산업경영시스템학회지)

Society of Korea Industrial and System Engineering (한국산업경영시스템학회)
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Multi-Dimensional Dynamic Programming Algorithm for Input Lot Formation in a Semiconductor Wafer Fabrication Facility

반도체 팹에서의 투입 로트 구성을 위한 다차원 동적계획 알고리듬

  • 방준영 (성결대학교 산업경영공학부) ;
  • 임승길 (성결대학교 산업경영공학부) ;
  • 김재곤 (인천대학교 산업경영공학과)
  • Received : 2016.01.25
  • Accepted : 2016.03.05
  • Published : 2016.03.31
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Abstract

This study focuses on the formation of input release lots in a semiconductor wafer fabrication facility. After the order-lot pegging process assigns lots in the fab to orders and calculates the required quantity of wafers for each product type to meet customers' orders, the decisions on the formation of input release lots should be made to minimize the production costs of the release lots. Since the number of lots being processed in the wafer fab directly is related to the productivity of the wafer fab, the input lot formation is crucial process to reduce the production costs as well as to improve the efficiency of the wafer fab. Here, the input lot formation occurs before every shift begins in the semiconductor wafer fab. When input quantities (of wafers) for product types are given from results of the order-lot pegging process, lots to be released into the wafer fab should be formed satisfying the lot size requirements. Here, the production cost of a homogeneous lot of the same type of product is less than that of a heterogeneous lot that will be split into the number of lots according to their product types after passing the branch point during the wafer fabrication process. Also, more production cost occurs if a lot becomes more heterogeneous. We developed a multi-dimensional dynamic programming algorithm for the input lot formation problem and showed how to apply the algorithm to solve the problem optimally with an example problem instance. It is necessary to reduce the number of states at each stage in the DP algorithm for practical use. Also, we can apply the proposed DP algorithm together with lot release rules such as CONWIP and UNIFORM.

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References

  1. Bang, J.-Y., An, K.-Y., Kim, Y.-D., and Lim, S.-K., A due-date based algorithm for lot-order assignment in a semiconductor wafer fabrication facility, IEEE Transactions on Semiconductor Manufacturing, 2008, Vol. 21, No. 2, pp. 209-216. https://doi.org/10.1109/TSM.2008.2000261
  2. Bang, J.-Y., Kim, Y.-D., and Choi, S.-W., Multiproduct Lot Merging-Splitting Algorithms for Semiconductor Wafer Fabrication, IEEE Transactions on Semiconductor Manufacturing, 2012, Vol. 25, No. 2, pp. 200-210. https://doi.org/10.1109/TSM.2012.2189784
  3. Boushell, T., Fowler, J., Keha, A., Knutson, K., and Montgomery, D., Evaluation of heuristics for a classconstrained lot-to-order matching problem in semiconductor manufacturing, International Journal of Production Research, 2008, Vol. 46, No. 12, pp. 3143-3166. https://doi.org/10.1080/00207540601001650
  4. Carlyle, M., Knutson, K., and Fowler, J., Bin covering algorithms in the second stage of the lot to order matching problem, Journal of the Operational Research Society, 2001, Vol. 52, No. 11, pp. 1232-1243. https://doi.org/10.1057/palgrave.jors.2601222
  5. Cha, M.-S. and Jang, J.-S., Effective Operation of SPC System in Semiconductor Manufacturing, Journal of the Korean Institute of Plant Engineering, 2009, Vol. 14, No. 4, pp. 95-103.
  6. Fowler, J., Knutson, K., and Carlyle, M., Comparison and evaluation of lot-to-order matching policies for a semiconductor assembly and test facility, International Journal of Production Research, 2000, Vol. 38, No. 8, pp. 1841-1853. https://doi.org/10.1080/002075400188627
  7. Glassey, C.R. and Resende, M.G.C., A scheduling rule for job release in semiconductor fabrication, Operations Research Letters, 1988, Vol. 7, pp. 213-217. https://doi.org/10.1016/0167-6377(88)90033-8
  8. Kim, J.-G. and Lim, S.-K., Order-lot pegging for minimizing total tardiness in semiconductor wafer fabrication process, Journal of the Operational Research Society, 2012, Vol. 63, No. 9, pp. 1258-1270. https://doi.org/10.1057/jors.2011.133
  9. Kim, J.-G., Lim, S.-K., and Bang, J.-Y., Lot-Order Assignment Applying Priority Rules for the Single-Machine Total Tardiness Scheduling with Nonnegative Time-Dependent Processing Times, Mathematical Problems in Engineering, 2015, Vol. 2015, Article ID 434653, p. 11.
  10. Knutson, K., Kempf, K., Fowler, J., and Carlyle, M., Lot-to-order matching for a semiconductor assembly and test facility, IIE Transactions, 1999, Vol. 31, No. 11, pp. 1103-1111. https://doi.org/10.1080/07408179908969911
  11. Lim, S.-K., Kim, J.-G., and Kim, H.-J., Simultaneous order-lot pegging and wafer release planning for semiconductor wafer fabrication facilities, International Journal of Production Research, 2014, Vol. 52, No. 12, pp. 3710-3724. https://doi.org/10.1080/00207543.2014.882025
  12. Lim, S.-K., Kim, J.-G., and Shin, Y., Optimal Three-Level Presort Loading of Commercial Bulk Mail in the Postal Service Industry, Journal of the Operational Research Society, 2015, Vol. 66, No. 6, pp. 1007-1022. https://doi.org/10.1057/jors.2014.68
  13. Ng, T.S., Sun, Y., and Fowler, J., Semiconductor lot allocation using robust optimization, European Journal of Operational Research, 2010, Vol. 205, No. 3, pp. 557-570. https://doi.org/10.1016/j.ejor.2010.01.021
  14. Seo, J.-C. and Bang, J.-Y., On-time Production and Delivery Improvements through the Demand-Lot Pegging Framework for a Semiconductor Business, Journal of the Society of Korea Industrial and Systems Engineering, 2014, Vol. 37, No. 4, pp. 126-133. https://doi.org/10.11627/jkise.2014.37.4.126
  15. Spearman, M.L., Woodruff, D.L., and Hopp, W.J., CONWIP : A pull alternative to kanban, International Journal of Production Research, 1990, Vol. 28, pp. 879-894. https://doi.org/10.1080/00207549008942761
  16. Wein, L.M., Scheduling semiconductor wafer fabrication, IEEE Transactions on Semiconductor Manufacturing, 1998, Vol. 1, pp. 115-130.
  17. Wu, T.W., Modular demand and supply pegging mechanism for semiconductor foundry, in Proceedings of the IEEE International Symposium on Semiconductor Manufacturing San Jose, Calif, USA., 2003, pp. 325-328.