Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
권호 표지
DOI QR코드

DOI QR Code

Memory window characteristics of vertical nanowire MOSFET with asymmetric source/drain for 1T-DRAM application

비대칭 소스/드레인 수직형 나노와이어 MOSFET의 1T-DRAM 응용을 위한 메모리 윈도우 특성

  • Lee, Jae Hoon (Department of Electronic Engineering, Incheon National University) ;
  • Park, Jong Tae (Department of Electronic Engineering, Incheon National University)
  • Received : 2016.01.25
  • Accepted : 2016.03.08
  • Published : 2016.04.30
Download PDF
⟨ Previous Next ⟩

Abstract

In this work, the memory window characteristics of vertical nanowire device with asymmetric source and drain was analyzed using bipolar junction transistor mode for 1T-DRAM application. A gate-all-around (GAA) MOSFET with higher doping concentration in the drain region than in the source region was used. The shape of GAA MOSFET was a tapered vertical structure that the source area is larger than the drain area. From hysteresis curves using bipolar junction mode, the memory windows were 1.08V in the forward mode and 0.16V in the reverse mode, respectively. We observed that the latch-up point was larger in the forward mode than in the reverse mode by 0.34V. To confirm the measurement results, the device simulation has been performed and the simulation results were consistent in the measurement ones. We knew that the device structure with higher doping concentration in the drain region was desirable for the 1T-DRAM using bipolar junction mode.

본 연구에서는 1T-DRAM 응용을 위해 Bipolar Junction Transistor 모드 (BJT mode)에서 비대칭 소스/드레인 수직형 나노와이어 소자의 순방향 및 역방향 메모리 윈도우 특성을 분석하였다. 사용된 소자는 드레인 농도가 소스 농도보다 높으며 소스 면적이 드레인 면적보다 큰 사다리꼴의 수직형 gate-all-around (GAA) MOSFET 이다. BJT모드의 순방향 및 역방향 이력곡선 특성으로부터 순방향의 메모리 윈도우는 1.08V이고 역방향의 메모리 윈도우는 0.16V이었다. 또 래치-업 포인트는 순방향이 역방향보다 0.34V 큰 것을 알 수 있었다. 측정 결과를 검증하기 위해 소자 시뮬레이션을 수행하였으며 시뮬레이션 결과는 측정 결과와 일치하는 것을 알 수 있었다. 1T-DRAM에서 BJT 모드를 이용하여 쓰기 동작을 할 때는 드레인 농도가 높은 것이 바람직함을 알 수 있었다.

Keywords

References

  1. Y. Nakagome, M. Aoki, S. Ikenaga, M. Horiguchi, S. Kimura, Y. Kawamoto and K. Itoh, "The Impact of Data-Line Interference Noise on DRAM Scaling." IEEE Journal of Solid-state circuits, vol. 23, no. 5, pp.1120-1127, Oct. 1988. https://doi.org/10.1109/4.5933
  2. H. Wann and C. Hu, "A capacitorless DRAM Cell on SOI Substrate." IEEE International Electron Devices Meeting, Washington, DC, USA, pp.635-638, 1993.
  3. M. Aoulaiche, E. Simoen, Ch. Cailat, N. Collaert, G.Groeseneken and M. Jurczak, "Reliability and Retention of Floating Body RAM on Bulk FinFET." Microelectronics and Solid State Electronics, vol. 1, no. 2, pp. 33-40, Feb. 2012.
  4. Wang G, Anand D, Butt N, Cestero A, more authors, "Scaling deep trench based eDRAM on SOI to 32nm and Beyond.", IEEE International Electron Devices Meeting, Baltimore, MD, pp. 1-4, 2009.
  5. S Okhonin, M Nagoga, J M Sallese, and P FazanA. "Capacitor- Less 1T-DRAM Cell." IEEE Electron Device Letters, vol. 23, no. 2, pp. 85-87, Oct. 2002. https://doi.org/10.1109/55.981314
  6. Yoshida E and Tanaka T, "A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory." IEEE Transactions on Electron Devices, vol. 53, no. 4, pp.692-697, Apr. 2006. https://doi.org/10.1109/TED.2006.870283
  7. J. Han, S. Ryu, S. Choi and Y. Choi, "Gate-Induced Drain-Leakage (GIDL) Programming Method for Soft-Programming-Free Operation in Unified RAM (URAM)" IEEE Electron Device Letters, vol. 30, no. 2, pp.189-191, Feb. 2009. https://doi.org/10.1109/LED.2008.2010345
  8. S. Okonin, M. Nagoga, E. Carman, R. Beffa and E. Faraoni. "New Generation of Z-RAM." IEEE Electron Devices Meeting, Washington, DC, pp.925-928, 2007.
  9. D. Moon, S. Choi, J. Han and Y. Choi, "A Study of BJT based Capacitorless 1T-DRAM with Consideration of Geometrical Dependence." Korean Conference on Semiconductors 17th, Daejeon, Korea, pp.7-8, 2010.
  10. M. Aoulaiche, N. Collaert, R. Degraeve, Z. Lu and B. Wachter, "BJT-Mode Endurance on a 1T-RAM Bulk FinFET Device." IEEE Electron Device Letters, vol. 31, no. 12, Dec. 2010.
  11. J. Goldberger, A. Hochbaum, R. Fan and P. Yang, "Silicon Vertically Integrated Nanowire Field Effect Transistors." Nano Letters, vol. 6, no. 5, pp.973-977, Mar. 2006. https://doi.org/10.1021/nl060166j
  12. D. Rideau, V. Quenette, D. Garetto, E. Dornel, M. Weybright, J. Manceau, O. Saxod and C. Tavernier, "Characterization & Modeling of Gate-Induced-Drain-Leakage with complete overlap and fringing model." IEEE International Conference on Microelectronic Test Structures (ICMTS), Hiroshima, pp.210-213, 2010.