전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

  • 제53권8호
  • /
  • Pages.66-75
  • /
  • 2016
  • /
  • 2287-5026(pISSN)
  • /
  • 2288-159X(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지
DOI QR코드

DOI QR Code

Voltage-Frequency-Island NoC를 위한 테이블 기반의 고장 감내 라우팅 기법

Table-Based Fault Tolerant Routing Method for Voltage-Frequency-Island NoC

  • 윤성재 (성균관대학교 정보통신대학) ;
  • 이창림 (성균관대학교 정보통신대학) ;
  • 김용석 (성균관대학교 정보통신대학) ;
  • 한태희 (성균관대학교 정보통신대학)
  • Yoon, Sung Jae (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Li, Chang-Lin (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Kim, Yong Seok (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Han, Tae Hee (College of Information & Communication Engineering, Sungkyunkwan University)
  • 투고 : 2016.03.16
  • 심사 : 2016.07.29
  • 발행 : 2016.08.25
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

반도체 공정 초미세화에 따라 에이징 (aging)과 공정 변이 (process variation)로 인한 칩에서의 물리적인 결함은 더욱 증가하고 있으며, 특히 금속 배선 스케일링 제한과 온 칩 데이터 통신량 증가에 따라 다수의 프로세서 코어로 구성된 네트워크-온-칩(Network-on-Chip, NoC)에서의 결함 감내 기법 연구가 활발히 진행되고 있다. 그러나 NoC에서 저전력 설계 기법으로 널리 채용되고 있는 VFI (Voltage-Frequency-Island)를 적용한 경우에서의 신뢰성 측면에 대한 연구가 부족한 실정이다. 본 논문에서는 신뢰성과 에너지 소모를 고려하여 VFI NoC에서 링크 고장이 발생하는 경우에도 정상적으로 통신을 유지할 수 있는 테이블 기반 라우팅 기법을 제안한다. 에너지 소모와 성능을 고려한 최적 경로와 고장 감내를 위한 우회 경로를 제공하며, 이때 우회 경로의 경우 필요한 최소한의 노드에만 라우팅 테이블을 저장하여 구현 복잡도를 완화하였다. 모의실험 결과를 통해 제안하는 기법은 전체 링크의 1%에서 고장이 발생하는 경우에도 정상적으로 통신함을 보였다. 또한 실시간으로 우회 경로를 탐색하는 고장 감내 라우팅 기법인 $d^2$-LBDR에 비해 링크에 고장이 발생하는 경우 평균 15.9%의 에너지 소모가 감소함을 보였으며, 실행 시간 측면에서는 평균 0.8% 감소하는 것을 확인 할 수 있었다.

Due to aggressive scaling of device sizes and reduced noise margins, physical defects caused by aging and process variation are continuously increasing. Additionally, with scaling limitation of metal wire and the increasing of communication volume, fault tolerant method in manycore network-on-chip (NoC) has been actively researched. However, there are few researches investigating reliability in NoC with voltage-frequency-island (VFI) regime. In this paper, we propose a table-based routing technique that can communicate, even if link failures occur in the VFI NoC. The output port is alternatively selected between best and the detour routing path in order to improve reliability with minimized hardware cost. Experimental results show that the proposed method achieves full coverage within 1% faulty links. Compared to $d^2$-LBDR that also considers a routing method for searching a detour path in real time, the proposed method, on average, produces 0.8% savings in execution time and 15.9% savings in energy consumption.

키워드

참고문헌

  1. L. Benini and G. De Micheli, "Networks on chips: A new SoC paradigm," Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002. https://doi.org/10.1109/2.976921
  2. W. Y. Jang, D. Ding, and D. Z. Pan, "A Voltage-Frequency Island Aware Energy Optimization Framework for Networks-on-Chip," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 1, no. 3, pp. 420-432, Sept. 2011. https://doi.org/10.1109/JETCAS.2011.2165756
  3. C,-L. Li, J. H. Lee, J.-S. Yang, and T. H. Han, "Communication-aware custom topology generation for VFI network-on-chip," IEICE Electronics Express, vol. 11, no. 18, pp. 1-8, Sept. 2014.
  4. U. Ogras, R. Marculescr, D. Marculescu, and E. Jung, "Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip," IEEE Trans. Very Large Scale Integration System, vol. 17, no. 3, pp. 330-341, March 2009. https://doi.org/10.1109/TVLSI.2008.2011229
  5. S. Herbert, S. Garg, and D. Marculescu, "Exploiting Process Variability in Voltage/Frequency Control," IEEE Trans. Very Large Scale Integration Systems, vol. 20, no. 8, pp. 1392-1404, Aug. 2009.
  6. A. DeOrio, D. Fick, V. Bertacco, and D. Sylvester, "A Reliable Routing Architecture and Algorithm for NoCs," IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 31, no. 5, pp. 726-739, May 2012. https://doi.org/10.1109/TCAD.2011.2181509
  7. J. D. Owens, W. J. Dally, R. Ho, D. N. Jayasimha, S. W. Keckler, and L. S. Peh, "Research Challenges for On-Chip Interconnection Networks," IEEE Micro, vol.27, no. 5, pp. 96-108, Sept.-Oct. 2007. https://doi.org/10.1109/MM.2007.4378787
  8. L. E. Bechtold, D. Redman, and B. Tawfellos, "Semiconductor Reliability Using Random and Wearout Failure Models," in Proc. of 2014 Annual Reliability and Maintainability Symp. (RAMS), pp. 1-6, Colorado Springs, CO, USA, Jan. 2014.
  9. D. Fick, A. DeOrio, G. Chen, V. Bertacco, D. Sylvester, and D. Blaauw, "A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs," in Proc. of Design, Automation and Test in Europe Conf. and Exhibition (DATE), pp. 21-26, Nice, France, April 2009.
  10. T. Schonwald, J. Zimmermann, O. Bringmann, and W. Rosenstiel, "Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures," in Proc. of 10th Euromicro Conf. Digital System Design Architectures, Methods and Tools (DSD), pp. 527-534, Lubeck, Germany, Aug. 2007.
  11. E. Wachter, A. Erichsen, A. Amory, and F. Moraes, "Topology-Agnostic Fault-Tolerant NoC Routing Method," in Proc. of Design, Automation and Test in Europe Conf. and Exhibition (DATE), pp. 1595-1600, Grenoble, France, March 2013.
  12. M. Ebrahimi, M. Daneshtalab, J. Plosila, and F. Mehdipour, "MD: Minimal path-based Fault-Tolerant Routing in On-Chip Networks," in Proc. of 18th Asia and South Pacific Design Automation Conf. (ASP-DAC), pp. 35-40, Yokohama, Japan, Jan. 2013.
  13. D. Lee, R. Parikh, and V. Bertacco, "Brisk and Limited-Impact NoC Routing Reconfiguration," in Proc. of Design, Automation and Test in Europe Conf. and Exhibition (DATE), pp. 1-6, Dresden, Germany, March 2014.
  14. M. Balboni, J. Flich, and D. Bertozzi, "Synergistic Use of Multiple On-Chip Networks for Ultra-Low Latency and Scalable Distributed Routing Reconfiguration," in Proc. of Design, Automation and Test in Europe Conf. and Exhibition (DATE), pp. 806-811, Grenoble, France, March 2015.
  15. R. Bishnoi, V. Laxmi, M. S. Gaur, and J. Flich, "d2-LBDR: Distance-Driven Routing to Handle Permanent Failures in 2D Mesh NoCs," in Proc. of Design, Automation and Test in Europe Conf. and Exhibition (DATE), pp. 800-805, Grenoble, France, March 2015.
  16. A. B. Kahng, B. Li, L. S. Peh, and K. Samadi, "ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration," in Proc. of Design, Automation and Test in Europe Conf. and Exhibition (DATE), pp. 423-428, Nice, France, April 2009.
  17. W. Liu, J. Xu, X. Wu, Y. Ye, X. Wang, W. Zhang, M. Nikdast, and Z. Wang, "A NoC Traffic Suite Based on Real Applications," in Proc. of IEEE Computer Society Annual Symp. VLSI (ISVLSI), pp. 66-71, Chennai, India, July 2011.
  18. Robert Mullins, Andrew West, and Simon Moore, "Low-Latency Virtual-Channel Routers for On-Chip Networks," in Proc. of the 31st annual International Symposium on Computer Architecture (ISCA), pp. 188-197, May 2004.
  19. Y. C. Chang, C. T. Chiu, S. Y. Lin, and C. K. Liu, "On the Design and Analysis of Fault Tolerant NoC Architecture Using Spare Routers," in Proc. of 16th Asia and South Pacific Design Automation Conf. (ASP-DAC), pp. 431-436, Yokohama, Japan, Jan. 2011.
  20. A. Prodromou, A. Panteli, C. Nicopoulos, and Y. Sazeides, "NoCAlert: An On-Line and RealTime Fault Detection Mechanism for Networkon-Chip Architectures," in Proc. of 45th Anuual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 60-71, Vancouver, Canada, Dec. 2012.
  21. Y. J. Yoon, N. Concer, M. Petracca, and L. Carloni, "Virtual Channels vs. Multiple Physical Networks: a Comparative Analysis," In Design Automation Conf. (DAC), pp. 162-165, Anaheim, USA, June 2010.
  22. "The Nangate Open Cell Library, 45nm FreePDK", available online at https://projects.si2.org/open eda.si2.org/projects/nangatelib/.