Journal of Advanced Navigation Technology (한국항행학회논문지)

The Korean Navigation Institute (한국항행학회)
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Research on Fault Tolerant Avionics Memory Design through Multi Level Cell Flash Memory Reliability Analysis

멀티 레벨 셀 플래시 메모리 신뢰성 분석을 통한 항공 전자장비용 내결함성 메모리 설계 연구

  • Jeong, Sang-gyu (3rd Sacheon team, Defense Agency of Technology and Quality) ;
  • Jun, Byung-kyu (3rd Sacheon team, Defense Agency of Technology and Quality) ;
  • Kim, Young-mok (3rd Sacheon team, Defense Agency of Technology and Quality) ;
  • Chang, In-ki (3rd Sacheon team, Defense Agency of Technology and Quality)
  • 정상규 (국방기술품질원 사천3팀) ;
  • 전병규 (국방기술품질원 사천3팀) ;
  • 김영목 (국방기술품질원 사천3팀) ;
  • 장인기 (국방기술품질원 사천3팀)
  • Received : 2016.06.21
  • Accepted : 2016.08.29
  • Published : 2016.08.30
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Abstract

Typical MLC NAND flash devices are considered less reliable than SLC NAND flash devices. Although raw bit error rate (RBER) of MLC flash had been considered approximately 1000times or more higher than that of SLC flash, recent research conducted on Google's data center shows that it is much lower than such expectation. Based on the research, we devised In Drive Data Duplication (IDDD) scheme that efficiently exploit MLC flash's sufficient capacity to improve its data reliability without structural complexity increment using SSD intrinsic firmware layer, and showed the data reliability expectation of MLC flash could be significantly higher than that of SLC flash from measured and calculated error rates. Even though RBER of SLC flash was lower than that of MLC flash in 44 out of 48 cases we studied, applying IDDD scheme, RBER of MLC flash was became lower than that of SLC in all 48 cases and uncorrectable bit error rate (UBER) of MLC flash was became lower than that of SLC flash in 45 out of 48 cases.

일반적으로 MLC NAND 플래시 저장장치는 SLC NAND 플래시 기반의 장치에 비해 정보 신뢰성이 낮은 것으로 평가된다. MLC 플래시는 SLC 플래시 보다 약 1000배 이상의 RBER (raw bit error rate)을 갖는다고 평가되나 최근 Google 데이터 센터에서 수집된 결과로부터 수행된 연구를 통해 실제 RBER은 이보다 훨씬 낮은 것으로 확인되었다. 이런 연구 결과를 바탕으로 우리는 MLC 플래시의 여유 저장 공간과 SSD 내부에 존재하는 Firmware 층을 활용하여 하드웨어적 구조 복잡성의 증가 없이 정보 신뢰성을 향상시키는 방법인 IDDD (in drive data duplication) 방식을 고안하였고 실 측정결과와 계산을 통해 MLC 플래시의 정보 신뢰성이 SLC 플래시 대비 상당히 높아질 수 있음을 보였다. 우리가 연구한 총 48개 상황 중 44개의 상황에서 SLC 플래시의 RBER이 MLC 플래시보다 낮았음에도 불구하고 IDDD방식을 적용함으로써 48개의 모든 상황에서 MLC 플래시의 RBER이 SLC 플래시보다 낮으며, 43개의 상황에서 UBER (uncorrectable bit error rate) 또한 SLC 플래시 대비 낮음을 보였다.

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References

  1. S. S. Rizvi, and T. S. Chung, "Flash SSD vs HDD: High performance oriented modern embedded and multimedia storage systems," in 2010 2nd International Conference on Computer Engineering and Technology (ICCET), Chengdu: China, pp. 297-299, 2010.
  2. N. Agrawal, and V. Prabhakaran, "Design tradeoffs for SSD performance," in USENIX Annual Technical Conference. San Diego: CA, pp. 57-70, 2008.
  3. R. Dan, and R. Singer, Implementing MLC NAND flash for cost-effective, high-capacity memory, M-systems, Kfar Saba, White paper 91-SR-014-02-8L, 2003.
  4. K. Yoshikawa, "Impact of cell threshold voltage distribution in the array of flash memories on scaled and multilevel flash cell design," in 1996 Symposium on VLSI Technology, Honolulu: HI, pp. 240-241, 1996.
  5. B. Schroede, and R. Lagisetty, A. Merchant. "Flash reliability in production: the expected and the unexpected," in 14th USENIX Conference on File and Storage Technologies (FAST 16), Santa Clara: CA, pp. 67-80, 2016.
  6. K. H. Park, "Reliability and performance enhancement technique for SSD array storage system using RAID mechanism," in 9th International Symposium on Communications and Information Technology 2009 (ISCIT 2009), Icheon, pp. 140-145, 2009.
  7. M. Balakrishnan, "Differential RAID: rethinking RAID for SSD reliability," ACM Transactions on Storage (TOS), Vol. 6, No. 2, pp. 55-59, July 2010.
  8. J. Elerath, and M. Pecht, "Enhanced reliability modeling of RAID storage systems," in 7th Annual IEEE/IFIP International Conference on Dependable Systems and Network 2007 (DSN'07), Edinburgh; Netherlands, pp. 175-184. 2007.
  9. B. Chen, X. Zhang, and Z. Wang, "Error correction for multi-level NAND flash memory using Reed-Solomon codes," in Workshop on Signal Processing Systems 2008 (SiPS 2008), Washington: DC, pp. 94-99, 2008.
  10. R. S. Liu, C. L. Yang, and W. Wu, "Optimizing NAND flash-based SSDs via retention relaxation," in Proceedings of the 10th USENIX conference on File and Storage Technologies (FAST'12), San Jose: CA, pp.125-135, 2012.
  11. K. Zhao, "LDPC-in-SSD: making advanced error correction codes work effectively in solid state drives," in Presented as part of the 11th USENIX Conference on File and Storage Technologies (FAST 13), San Jose: CA, pp. 243-256, 2013.
  12. A. Kawaguchi, S. Nishioka, and H. Motoda, "A Flash-Memory Based File System," in Proceedings of the USENIX 1995 Winter Technical Conference, New Orleans: LA, pp. 155-164, 1995.
  13. R. Micheloni, A. Marelli, and K. Eshghi, SSD Architecture and PCI Express Interface, in Inside Solid State Drives (SSDs), 1st ed. Dordrecht: Springer, ch. 2, pp. 19-45, 2012.