A Modified Switched-Diode Topology for Cascaded Multilevel Inverters

Abstract

In this paper, a single phase modified switched-diode topology for both symmetrical and asymmetrical cascaded multilevel inverters is presented. It consists of a Modified Switched-Diode Unit (MSDU) and a Twin Source Two Switch Unit (TSTSU) to produce distinct positive voltage levels according to the operating modes. An additional H-bridge synthesizes a voltage waveform, where the voltage levels of either polarity have less Total Harmonic Distortion (THD). Higher-level inverters can be built by cascading MSDUs. A comparative analysis is done with other topologies. The proposed topology results in reductions in the number of power switches, losses, installation area, voltage stress and converter cost. The Nearest Level Control (NLC) technique is employed to generate the gating signals for the power switches. To verify the performance of the proposed structure, simulation results are carried out by a PSIM under both steady state and dynamic conditions. Experimental results are presented to validate the simulation results.

I. INTRODUCTION

Employing multilevel inverters (MLIs) for medium to high voltage and high power applications has been gaining importance since the mid 1970s. The main features of MLIs are their abilities in reducing the dv/dt in the synthesized output phase voltage waveform and a reduction of the THD. In contrast, multi pulse converters utilize magnetic components to achieve desired voltage levels in the output voltage waveforms. The presence of magnetic components, their complexity of control, prone to failure, amount of loss and size make them inferior. The evolution of multilevel inverters started with the three classical structures namely the diode clamped multilevel inverter, also known as neutral point clamped (NPC), the capacitor-clamped multilevel inverter or flying capacitor (FC), and the cascade H-bridge (CHB). Further, many topologies have emerged and find their potential applications in distributed energy systems, flexible alternating current transmission (FACTS) and high voltage DC (HVDC) transmission [1], [2]. The classical CHB is remold into two power cells, each of which consist of a half bridge and a source for renewable energy applications [3].

The MLIs use power semiconductor switches in significant numbers to synthesize a smoother stair case output voltage waveform. The main issues to cope with in MLIs to generate multilevel voltages, are circuit complexity, control and efficiency. A reduction of the power electronic switches in MLI topologies has created a huge interests in academia and in the industry. Reduced switch count MLI topologies have been categorically presented and some of them are symmetrical and some of them are asymmetrical [4].

In brief, these emerging topologies are classified as Type-I, Type-II, Type-III and hybrid MLIs on the basis of their structures as shown in Fig.1. In Type III topologies, the basic unit is derived from a three leg 2-level inverter. This derived unit can generate 5-levels in output voltage using two equal DC sources, i.e. symmetrical mode [7]. The algorithms are proposed to define the magnitude of the DC sources i.e. asymmetric mode. The basic unit in the asymmetrical mode requires both unidirectional and bidirectional switches [8]. In the symmetrical mode, the generalization of higher level generation needs only unidirectional switches [9]-[11]. By incorporating two additional switches to the basic unit [7], the maximum voltage levels can be achieved [12]. The basic unit needs bidirectional switches in the middle leg in the asymmetric mode. The basic unit uses a switch surrounded by four diode bidirectional configurations and these basic units are cascaded [13]. The basic unit is reconstructed in a cross connected manner so as to reduce the voltage stress [14]-[16].

Fig. 1.Classification of emerging MLI topologies with reduced witch count.

In Type I and II topologies, the inverter has a level selection (LS) part to produce an even number of unidirectional voltage levels. They are also equipped with an H-Bridge for polarity reversal to synthesize an odd number of output voltage levels of either polarity. The Type I LS part consists of an Auxiliary (AUX) switch of a bidirectional nature, formed by a switch surrounded by four diodes [5], [6].

In Type II topologies, the inverter has only switches [17]-[22] or switches and diodes [23]-[25] in its level selection part. Bi-directional switches are used in a series connected sub-multilevel inverter to synthesize various voltage levels [17]. The gate drives requirement for each bidirectional switch are the same as a unidirectional switch at the cost of doubling the number of IGBTs / MOSFETs.

A Modified Topology is proposed to reduce the switch count, as a staircase type [18], by employing all of the unidirectional switches. The reduction in the switch count is further assessed with a modified level selection part by connecting DC sources in series/parallel [19]. A multi cell arrangement is presented to reduce the bidirectional count requirement in the level selection part [20]. The bidirectional switches are further reduced by replacing them with unidirectional switches for the top and bottom arms of the level section part [21]. A basic unit has been constructed and further cascaded to get more voltage levels in the output [22]. A tremendous decrement in the switch count is achieved in the switched-diode topologies [23]-[26], where only unidirectional switches are employed in the level selection part along with one diode in each cell. The hybrid structures are proposed for single phase [27] and three phase [28], [29], [34] operations.

A modified switched diode unit (MSDU) is constructed in this paper. This MSDU enables the advantages of a reduced switch count, a reduced diode count, improvement in efficiency and a simpler control. The proposed MLI is tested with the low switching frequency NLC control technique.

 

II. PROPOSED MODEL

The proposed MLI is a Type III topology and it is made up of three essential parts described as follows:

A. Modified Switched Diode Unit (MSDU)

The MSDU is made up of three unidirectional IGBT switches S1, S2, S3, one diode D1 and three isolated DC sources V1, V2, V3 as depicted in Fig. 2(a). The switching states of the power switches for the MSDU are shown in Table I, which shows that it can generate three different levels of 0, (V1 + V3) and (V1 + V2 + V3) in the output voltage and that these three levels are of positive polarity. The occurrence of short circuits caused by the power switch pair (S2, S3) should be avoided by not turning ON, while S1 is in OFF. In order to generate more voltage levels it is possible to cascade the MSDUs, enabling it for higher voltage applications. The output voltage of each unit MSDU is indicated by Vo1, Vo2…VoP.

Fig. 2.Proposed multilevel inverter units. (a) Modified switch diode unit (MSDU) and (b) Twin switch twin source unit (TSTSU)

TABLE ISWITCHING STATES OF MSDU

B. Twin Switch Two Source Unit (TSTSU)

The TSTSU is made up of two isolated DC sources Va, Vb and two unidirectional power IGBT switches Sa, Sb as depicted in Fig. 2(b). The switching states of the power switches for the TSTSU are shown in Table II, which can generate two different levels of Va, Va+Vb in the output voltage. These two levels are of positive polarity. Short circuits can be avoided by not turning on both of the switches Sa, Sb at the same instant. Doing so may lead to a circulating current in the TSTSU, which may damage the power switches. The TSTSU is connected in series with the MSDU so that all of the required voltage levels can be synthesized.

TABLE IISWITCHING STATES OF TSTSU

C. Polarity reversal part (Conventional H-bridge):-

A conventional H-bridge having four power IGBT switches (T1-T4) can produce three different levels, which includes the zero, positive and negative levels of the applied voltage at the bridge input. The voltage Vb across the terminals of the bridge input have only positive voltage levels which are given by:

By adding a H-bridge in cascaded connection, as depicted in Fig. 3, the positive levels are enabled through the bridge, when the IGBTs (T1, T4) are ON. Then the load voltage VL is equal to +Vb. When the IGBTs (T2, T3) are ON, the load voltage VL is equal to -Vb. The zero voltage level is done by turning on either (T1, T2) or (T3, T4).

Fig. 3.Proposed cascaded multilevel inverter topology.

 

III. OPERATING MODES

The feature of the proposed MLI is its ability to operate in both symmetrical and asymmetrical modes. In this section the mathematical expressions of various parameters are derived, which are helpful in the comparative analysis to make it realizable.

A. Symmetrical Mode

In this mode, the magnitude of the DC voltage sources in each unit of the MSDU and the TSTSU are set equal.

The number of levels ‘L’ produced in this mode can be related mathematically with the number of isolated DC sources ‘S’ used by the equation:

If ‘P’ number of MSDUs is connected in cascade, the number of sources used ‘S’ and the number of levels ‘L’ produced in this mode of operation by the proposed inverter, along with the number of IGBTs ‘G’ used and the number of additional power diodes ‘D’ used are given by the following equations, respectively:

All of the switches in the proposed topology are unidirectional power switches. Hence, the number of gate driver circuits ‘GD’ is equal to the number of IGBTs G, which is expressed as:

The maximum output voltage produced VL, max is given by:

The voltage and current ratings of the switches in a multilevel converter play an important role in the cost and realization of the converter. In the proposed topology, the currents of all the switches are equal to the rated current of the load. However, this is not the case for the voltage. The Peak Inverse Voltages (PIV) from Fig. 2 is mathematically expressed as follows:

The total PIV of the proposed inverter is the sum of all the PIVs in the MSDU, TSTSU and H-bridge, which is expressed as:

Symmetrical multilevel inverters have attractive features in terms of modularity in construction, ease of control and the ready availability of equal DC sources.

B. Asymmetrical Mode

Employing different dc voltages with proper ratios can improve the output voltage total harmonic distortion (THD), which improves the power quality. In this mode, the magnitude of the DC sources used in the TSTSU and the first MSDU are same, while in the other MSDUs are maintained at double the value of that in the first unit, for the generalized proposed structure illustrated in Fig 3.

Equations (6)-(8) are also valid for the asymmetrical mode, as per equation (14).

The asymmetrical MLIs have an edge over the symmetrical structures in generating a larger number of voltage levels in the load output voltage. Hence, the quality of load voltage waveform is further improved.

 

IV. COMPARATIVE ANALYSIS

Various topologies have been presented for MLIs. The asymmetrical topologies presented in [6] and [20] are the best in synthesizing more levels in inverter output voltage with the same number of DC sources used in the symmetrical modes. The realization of asymmetrical MLIs, which has to be provided from DC voltage sources with different values, can be very costly and difficult. As mentioned before, in the symmetric multilevel inverters, the values of all of the DC voltage sources are equal leading for easier realization possibility and lower design cost. However, the symmetric topologies can produce a lower number of voltage levels in comparison with the asymmetric topologies.

To have the same condition, the proposed topology in the symmetric mode P1 is compared with the symmetric MLI topologies presented in [3], [5]-[6], [8], [13]-[14], [17]-[19], [22], [24] and with the symmetrical CHB [31]. The asymmetrical operation of the proposed multilevel inverter P2 is also compared along with the asymmetrical operation of the topology in [22] represented as ‘A’ in Fig 4 (a)-(e). The comparison is done in view of optimizing the number of IGBTs, the number of diodes used, the number of driver circuits, the number of sources used and the PIV (p.u.) with an increasing number of levels in the output voltage is presented in Fig. 4 (a)-(e).

Fig. 4.Comparison of parameters with level count ‘L’. (a) IGBT count ‘G’, (b) Gate Driver count ‘GD’(c) Diode count ‘D’, (d) Source count ‘S’, and (e) PIV p.u..

The Fig. 4(a) reveals the fact that the proposed inverter is the one with the minimum number of switches. Fig. 4(b) shows the gate drive count is minimum for proposed inverter in both the symmetric mode P1 and the asymmetrical mode P2. From Fig. 4(c) it can be concluded that the proposed inverter is the best choice when it comes to usage to achieve a minimum number of diodes. Fig. 4(d) shows that all of the symmetrical converters generate a number of levels that is double the number of sources, while the symmetrical mode requires fewer sources for the same number of levels generation. Fig. 4(e) shows the PIV of the proposed inverter which is nearer to [31], [22]. However the topologies in [14]-[16] are the best since they are specially designed to reduce the PIV as a compromise against a larger number of IGBTs than the proposed topology. By changing the modulation index ‘m’ the level count ‘L’ is changed and as a result, the %THD and the switching loss are also changed. The variation of the %THD, switching loss and Level count ‘L’ with the modulation index ‘m’ are shown in Fig 5(a)-(b) for the symmetrical and asymmetrical modes, respectively. It is observed that for both the modes L and the switching loss increases, the % THD decreases with increases in m. The ratio of the level count to the IGBT count (L/G) should be optimum. A comparison is done with the recently proposed topologies [22], [27]-[29], [34] for the single phase under both the symmetrical and asymmetrical modes of operation as presented in Table 3. This shows that the proposed MLI has an optimum L/G ratio for both of the modes.

Fig. 5.Variation of %THD, Switching loss and Level count with change in modulation index ‘m’.(a) symmetrical 17 level operation and (b) Asymmetrical 23 level operation.

TABLE IIICOMPARISON OF RECENT TOPOLOGIES FOR OPTIMUM L/G RATIO ON SINGLE PHASE BASIS

 

V. CONTROL SCHEME

The proposed MLI can operate at both the fundamental switching frequency and high switching frequency PWM. A wide variety of modulation and control methods have been developed for multilevel converters such as sinusoidal pulse width modulation (SPWM) [10-11],[30], selective harmonic elimination (SHE-PWM), space vector modulation (SVM) etc. The complexity of the SVM algorithm increases with the number of levels [30]-[32]. In the SHE, the offline computation of a large amount of switching angles and storing them is a tedious task for employing the proposed MLI.

The NLC technique [2], [34] facilitates the synthesizing of a very high number of voltage levels by approximating the amplified voltage reference (K*Vref) to the closest generable voltage level of the converter, as depicted in Fig. 6(a)-(b). The corresponding mathematical equations are given by:

Fig. 6.Nearest level control technique. (a) block diagram and (b) Graphical representation.

 

VI. SIMULATION RESULTS

The proposed MLI is simulated using PSIM 9.3 for both the symmetrical and asymmetrical modes. As shown in Fig. 7(a) and Fig. 8(a), one TSTSU and two MSDUs are used. In the symmetrical mode, all of the DC source voltages are kept at 15V. Meanwhile, in the asymmetrical mode, DC sources of 15V are used in the TSTSU and in the first MSDU and 30V are used in the second MSDU.

Fig. 7.Simulation results in symmetrical mode. (a) Symmetrical mode connection diagram and (b) Load voltage and current waveforms.

Fig. 8.Simulation results in asymmetrical mode. (a) Asymmetrical mode connection diagram and (b) Load voltage and current waveforms.

The conducting switches are listed in Table 4 and Table 5 for operation of both modes, respectively. The results are obtained with a resistive-inductive (R-L) load with R=110Ω, L=80mH at a modulation index of m=1.0. The load voltage and current waveforms are given in Fig. 7(b) and Fig. 8(b) of both modes, respectively. It can be observed that the symmetrical mode gives 17 levels and that the asymmetrical mode gives 23 levels in its output voltage. The phase voltage THD obtained in the symmetrical mode is 4.84% and in asymmetrical mode it is 3.55%.

TABLE IVSWITCHING STATES FOR PROPOSED 17-LEVEL SYMMETRICAL MLI

TABLE VSWITCHING STATES FOR PROPOSED 23-LEVEL ASYMMETRICAL MLI

To analyze the dynamic behavior of the proposed MLI, a step change in the modulation index ‘m’ is considered for both the symmetrical and asymmetrical modes of operation. A step change of m=0.5 having a duration of 1 cycle (i.e.20ms) is applied at=0.02 sec, and another step change of m=0.1 having a duration of 1 cycle is applied at t=0.04 sec as shown in Fig. 9(a). The level count ‘L’ gets reduced to 3 from 17 in the load voltage for respective step changes in the symmetrical mode as shown in Fig. 9(b). The variations of the load voltage and the current during step changes in the asymmetrical mode are shown in Fig. 9(c).

Fig. 9.Dynamic response (a) Step changes in modulation index ‘m’, (b) Load voltage and current waveforms in symmetrical mode and (c) Load voltage and current waveforms in asymmetrical mode.

 

VII. EXPERIMENTAL RESULTS

To validate the simulation and theoretical results, a low power, single-phase, prototype is built as shown in Fig. 10. The NLC control algorithm is implemented digitally by using a DSP TMS32F28335 with code composer studio 5.3.0. The inverter is built with IRG4PH50UD IGBTs and RURP15120 ultrafast recovery Diodes as switching devices. The amplification and the isolation from the power circuit is provided by a driver TLP250. The prototype is tested with a resistive-inductive load of R=110Ω and L=72mH. A power scope of TEKTRONIX, Model No. TPS2024B, is used for recording the harmonic content.

Fig. 10.Experimental set-up in the laboratory.

In the symmetrical mode of operation, the proposed MLI is supplied by eight isolated DC voltage sources of 15V, to synthesize an inverter output voltage peak value of ±120 V through 17 levels in steps of 15V at 50Hz. The voltage and current waveforms are shown in Fig. 11(a). A harmonic analysis of the voltage waveform is depicted in Fig. 11(c). It shows that the %THD is 5.03%.

Fig 11.Load Voltage (50V/div) and current (1A/div) waveforms for modulation index m=1.0 (a) Symmetrical mode 17-level operation and (b) Asymmetrical mode 23-level operation. Harmonic spectrum of load voltage waveform. (c) Symmetrical mode 17-level operation and (d) Asymmetrical mode 23-level operation.

In the asymmetrical mode of operation, the TSTSU, and the first MDSU are supplied from isolated DC sources of 15V, and the second MDSU is supplied by isolated DC sources of 30V to achieve an inverter output voltage peak value of ±165V through 23 levels in steps of 15V at 50Hz. The voltage and current waveforms are shown in Fig. 11(b). A harmonic analysis of the voltage waveform is depicted in Fig. 11(d), it shows that the %THD is 4.09%.

The dynamic behavior of the proposed MLI is assessed by considering the step changes in the modulation index ‘m’. The load voltage VL of the inverter and the level count ‘L’ change according to the step change in the modulation index ‘m’ as described by (21). Variations in the load voltage VL and load current IL waveforms for step changes in the modulation index ‘m’ for 0.5 and 0.1 are presented in Fig. 12(a) and (c) for the symmetrical mode, and in Fig. 12(b) and (d) for the asymmetrical mode, respectively.

Fig 12.Response of proposed MLI to step changes in modulation index ‘m’.(a),(c) Voltage (50V/div) and current (1A/div) waveforms for symmetrical mode 17-level operation and (b),(d) Voltage (50V/div) and current (1A/div) waveforms for asymmetrical mode 23-level operation.

 

VIII. CONCLUSIONS

A modified switched-diode topology for a cascaded multilevel inverter has been proposed and a comparative analysis has been done in view of different aspects such as the number of switching components, number of gate drivers, number of sources, and PIV with respect to the level count for both the symmetrical and asymmetrical operating modes. Simulation results are presented and validated by conducting experiment on the proposed inverter in both operating modes under steady state and dynamic conditions. The obtained experimental results show the ability of the proposed inverter to generate all of the levels with a reduced number of switches.