Performance Evaluations of Four MAF-Based PLL Algorithms for Grid-Synchronization of Three-Phase Grid-Connected PWM Inverters and DGs

Abstract

The moving average filter (MAF) is widely utilized to improve the disturbance rejection capability of phase-locked loops (PLLs). This is of vital significance for the grid-integration and stable operation of power electronic converters to electric power systems. However, the open-loop bandwidth is drastically reduced after incorporating a MAF into the PLL structure, which makes the dynamic response sluggish. To overcome this shortcoming, some new techniques have recently been proposed to improve the transient response of MAF-based PLLs. In this paper, a comprehensive performance comparison of advanced MAF-based PLL algorithms is presented. This comparison includes HPLL, MPLC-PLL, QT1-PLL, and DMAF-PLL. Various disturbances, such as grid voltage sag, voltage flicker, harmonics distortion, phase-angle and frequency jumps, DC offsets and noise, are considered to experimentally test the dynamic performances of these PLL algorithms. Finally, an improved positive sequence extraction method for a HPLL under the frequency jumps scenario is presented to compensate for the steady-state error caused by non-frequency adaptive DSC, and a satisfactory performance has been achieved.

I. INTRODUCTION

The three-phase phase-locked loop (PLL) technique is widely used for accurate estimation of the phase-angle, frequency, and sequence components extraction of the grid voltages in power systems, which is crucial for the grid-integration of distributed generation (DG) systems, such as wind, PV, and flexible ac transmission systems (FACTS), as well as active power filters (APFs) [1]-[3]. However, a great challenge associated with PLLs is obtaining accurate and fast estimations of the phase angle and frequency under adverse grid voltage disturbance scenarios. According to European standard EN50160, typical voltage disturbance scenarios include voltage sag, flicker, harmonics distortion, phase-angle and frequency jumps, dc offsets and noise contaminations [4]. To achieve accurate grid-synchronization under grid disturbances, several new structures to enhance the performance of PLLs have been presented [5]-[14].

In addition to the use of these new structures, a more general approach to improving the performance of a PLL is to combine them with filters [15]-[36], such as extended Kalman filters (EKFs) [15], space vector filters (SVFs) [16], notch filters [17], digital filters [18], complex-coefficient filters (CCF) [19], the delayed signal cancellation (DSC) block method [20]-[24], and MAF-based methods [25]-[36]. Among these filtering techniques, DSC and MAF show similar filtering characteristics. They can almost completely block specific frequency signals. From the view point of the discrete implementation of DSC and MAF, they are both composed of a number of particular delay blocks. However DSC is often used to improve the performance of a PLL under adverse grid conditions [23]. In [24], a comparison of MAF and DSC, as well as their derived methods, was presented in terms of the dynamic response, steady-state performance, required data size, and harmonic and noise immunity capability. In [25], the dqCDSC-PLL and the MAF-PLL algorithms were shown to be mathematically equivalent under certain conditions.

The MAF technique is the most popular and widely used technique (it can be used in the natural abc coordinates, the αβ coordinates and the dq coordinates) owing to its simple digital realization, low computational burden, and effectiveness under grid disturbance conditions [26]. However, the open-loop bandwidth of a PLL is drastically reduced after incorporating a MAF into its structure. This may be beneficial in terms of stability, but it degrades the dynamic performance of the PLL. To solve this problem, some advanced MAF-based PLL algorithms have been presented [27]-[36].

In [26], a detailed analysis and design guideline of a MAF-PLL and its frequency adaptive implementation were presented, in which a performance comparison of the well-tuned MAF-based PLL with a PI controller and the PID controller was presented. It was shown that the PID-type MAF-PLL has a higher bandwidth, which means a faster dynamic response while decreasing the noise immunity and disturbance rejection capability. In [27] a critical comparison between PLLs and FLLs based on the MAF, CDSC and DSOGI filtering techniques was presented. It is shown that these kinds of filtering techniques can all effectively remove noise, harmonics and negative sequence, and that the initial phase angle detector with a MAF-based PLL shows the best performance under frequency and phase angle jump scenarios. A novel MAF-based PLL consisting of a frequency detector and an initial phase was presented in [28], in which the effect of discrete sampling on the MAF is analyzed and a linear interpolation is employed to enhance the performance of the MAF. In [29], an enhanced MAF (EMAF) algorithm was presented, which shows superior performance in terms of response time, transient overshoot, computational load, harmonics and noise immunity compared with the DSC algorithm.

In [30], a MAF and a weighted least squares estimation (WLSE) scheme based PLL was proposed, in which the MAF was used to filter out all of the odd-order harmonics and to help the WLSE detect the fundamental positive-sequence components accurately even under heavily distorted grid conditions. In [31], a MAF was used as a perfiltering stage in the dq-frame (PMAF-PLL) to remove the negative sequence and odd-order harmonic components, and then an enhanced method was proposed to improve the steady-state performance under frequency varying conditions. Furthermore, a small-signal model of the PMAF-PLL was presented, and it has been shown that the PMAF-PLL and the space-vector Fourier transform-based PLL (SVFT-PLL) are theoretically equivalent. In [32], a novel design of a low-gain PLL introducing an adaptive MAF before the loop-filter (LF) and its discrete domain model were presented. Compared with the conventional high gain SRF-PLL, the phase and voltage frequency error is reduced and the phase angle tracking is faster and more accurate.

In [33], a quasi-type-1 PLL (QT1-PLL) was presented. In this structure, the proportional integral (PI) controller was replaced by a simple gain. Thus, a larger open-loop bandwidth can be realized. However, the QT1-PLL cannot filter out the dc offset or even order harmonics. In order to tackle this problem, a hybrid PLL (HPLL) was presented in [34]. In this HPLL, delayed signal cancellation (DSC) is used in the αβ axis to eliminate the dc offset and even order harmonics. The phase error compensation (PEC) method was adopted for the QT1-PLL and HPLL to achieve zero steady-state error when frequency jumps occur. In [35], a MAF-PLL with a phase-lead compensator (MPLC-PLL) was presented. With a phase-lead compensator in the control loop, the dynamic response of the standard MAF-PLL can be effectively improved without deteriorating its disturbance rejection capabilities. A differential MAF-PLL (DMAF-PLL) was presented in [36]. With this approach, a special loop filter structure was used to eliminate the negative sequence 2nd order harmonics in order to reduce the window length of the MAF and to significantly improve the dynamic performance of the PLL.

The main objective of this paper is to provide performance evaluations (including the transient response and disturbance rejection capabilities) of four MAF-based PLLs (QT1-PLL, HPLL, MPLC-PLL, and DMAF-PLL) by analytical comparisons and experimental results. The steady-state and dynamic performances of these algorithms are compared in terms of settling time, phase tracking error and overshoots. Experimental results show that the QT1-PLL and MPLC-PLL lack the rejection capabilities of dc offset and even order harmonics. These are the main shortcomings of these algorithms, which can be overcome by employing a DSC in the αβ coordinates or a MAF in the abc coordinates. In the last section, an amplitude error compensation (AEC) method is proposed to achieve zero steady-state error for the positive sequence amplitude estimation under frequency jump conditions. Extensive experimental results are provided for validation. This facilitates the practical application of these MAF-based PLLs for achieving accurate grid-synchronization of the three-phase grid-connected PWM inverters and distributed generators (DGs) in smartgrids.

 

II. OVERVIEW OF MAF-BASED PLLS

In this Section, a brief overview of the MAF is outlined. In addition, four MAF-based PLL algorithms and discrete models are described.

A. Moving Average Filter (MAF)

The transfer function of the MAF can be obtained simply in the s-domain and the z-domain as [19]:

where Tω represents the window length. In addition, Tω=NTs, Ts is the sample time that is set to 0.0001 s, and N is an integer. Transfer function (1) shows that the MAF requires a time equal to its window length to gather data and reach steady-state conditions. Therefore, a smaller window length results in a faster dynamic response of the MAF-based PLL algorithms.

As shown in (2), the application of a MAF in the z-domain is computationally efficient with simple delay blocks [26], as shown in Fig. 1. From the aforementioned analysis, the delay factor N can be set as a constant to remove the fixed frequency signal or as frequency adaptive according to the equation N=round (mπ/ω0Ts), in which the MAF is used to remove the odd-order harmonic for m=1, and to remove the dc offset for m=2. The detailed discrete-time realization was discussed in [26].

Fig. 1.The realization of MAF in z-domain.

Using the transfer functions (1) and (2), a bode diagram of a MAF and a low-pass filter (LPF) is shown in Fig. 2, in which Tω is set to 0.01 s (N=100) and the corresponding cutoff frequency in the LPF is 200 rad/s. This shows that the even order harmonics are effectively eliminated since the MAF has a high attenuation at these harmonic frequencies.

Fig. 2.Bode diagram comparison of MAF and first-order LPF.

B. QT1-PLL

Fig. 3 shows the general structure of the QT1-PLL, in which a MAF cascading a proportional controller act as the loop filter. Thus, from the view point of the structure, the QT1-PLL is a type-I PLL, which has a high stability margin compared with the typical MAF-PLL (in which a MAF and a PI controller act as the loop filter). However, the main disadvantage of a conventional type-I PLL lies in the phase tracking error under the grid frequency step condition.

Fig. 3.Block diagram of the QT1-PLL proposed in [33].

As shown in Fig. 3, three-phase grid voltages with a dc offset and harmonics can be defined as (here, the symmetrical load is taken into consideration, which corresponds to the -5th, +7th, -11th, and +13th order harmonics):

where are the amplitude and phase-angle of the hth harmonic components of the positive- (negative-) sequence of the input voltages, respectively. Va,dc, Vb,dc and Vc,dc are the dc offset added to the phase-a, phase-b and phase-c voltages, respectively.

Applying the Clarke transformation to (3), vα and vβ can be written as:

Then, applying the Park transformation to (4), vd and vq can be written as:

where are the oscillating terms caused by the grid voltage dc offset, where:

Under a quasi-locked condition (6) can be rewritten as:

where ωn is the fundamental angular frequency. Through the use of a MAF, the oscillating term f (ωn, 2ωn, 6ωn…) can be nearly removed. As mentioned earlier, a type-I PLL cannot achieve zero steady-state error when a frequency jump occurs. Hence, the phase tracking error of a type-I PLL under a frequency jump is expressed as [33]:

From equation (9), by selecting a sufficiently high value for kp, the phase error θe can be reduced to a very small value. However, this selection increases the PLL’s bandwidth remarkably which is not preferred under distorted and unbalanced grid voltage conditions. Notice that the average value of Δωo is equal to Δωi under locked conditions. Thus, as highlighted in Fig. 3, the phase tracking error is added to the output of the PLL to realize zero steady-state tracking error when a frequency jump occurs.

Fig. 4 shows a small signal model of the QT1-PLL. Since the s-domain transfer function has been expressed in [33], and considering practical application, the open-loop transfer function in the z-domain is expressed as:

Fig. 4.Small-signal model of the QT1-PLL [33].

As shown in (8), where the lowest oscillating frequency is ωn=50 Hz (in a 50 Hz system) by selecting Tω=0.02 s (i.e., N=200), the oscillating term can be removed completely. However, this selection may lead to a slow dynamic response. In order to achieve a tradeoff between the response speed and the filtering capability, the window length of the MAF is set to 0.01 s (i.e., N=100), which means that the MAF block cannot remove the fundamental frequency oscillation caused by the dc offset.

C. HPLL

Fig. 5 shows the general structure of the HPLL presented in [34] to overcome the main drawback of the QT1-PLL under dc offset and even-order harmonics scenarios. The main difference between the HPLL and the QT1-PLL is the application of delay signal cancellation (DSC) in the αβ axis (αβDSC). From Fig. 5, the αβDSC input signals are shown in (4). In order to filter out the dc offset (Vα,dc, Vβ,dc), the transfer function of the αβDSC applied in the HPLL can be defined in the Laplace-domain as [23]:

where T=0.02 s is the fundamental period of the grid voltages.

Fig. 5.Block diagram of the HPLL proposed in [34].

Substituting s=jω into (11), yields

From (12), it can be observed that the αβDSC2 operator has a unity gain and zero phase-shift at 50 Hz, and provides zero gain at zero frequency and all of the even order harmonic frequencies. This implies that GαβDSC2 blocks all of the dc offset and even order harmonics.

Therefore, vα and vβ can be written as:

Generally, GαβDSC2 can be designed to be frequency adaptive to achieve zero steady-state error under the frequency jump scenario. However, this feedback loop makes it rather difficult to ensure system stability. In order to solve this problem, the phase error is compensated by the PLL output. In order to compensate the phase shift caused by the GαβDSC2 block under frequency jump scenarios, assuming that Δωi is the deviation value of the grid frequency from the nominal grid frequency, the phase shift can be obtained as:

This phase-error can be easily compensated, as shown in Fig. 5, where kφ=T/4 can be selected.

The small signal model of the HPLL is shown in Fig. 6. The open-loop transfer function in the z-domain can be derived as:

Fig. 6.Small-signal model of the HPLL [34].

Since the dc offset has been removed by GαβDSC2, the lowest frequency that needs to be filtered out is 2ωn=100 Hz. Therefore, the window length of the MAF is set to Tω=0.01 s.

D. MPLC-PLL

Fig. 7 shows the general structure of the MPLC-PLL derived from the conventional MAF-PLL. The phase-lead compensator, as highlighted by Gc in Fig. 7, is applied in the control loop to effectively compensate the control delay caused by the MAF. The expressions of vd and vq are shown in (8). The transfer function of this compensator can be derived as:

where r is the attenuation factor, N is defined in equation (2), and k=(1-rN)/(1-r).

Fig. 7.Block diagram of the MPLC-PLL proposed in [35].

The small signal model of the MPLC-PLL is shown in Fig. 8. The open-loop transfer function in the z-domain can be derived as:

where the window length Tω is set to 0.01 (i.e., N=100, this selection also ignores the dc offset), and the attenuation factor r is set to 0.99.

Fig. 8.Small-signal model of the MPLC-PLL [35].

From Fig. 9, it can be observed that MAFs with and without the phase-lead compensator have similar filtering features at frequency f=100n (n=1, 2, 3, …). However, under other grid frequencies, especially at the frequency points A, B, C, D, and so on, a MAF with the phase-lead compensator may almost pass all of these frequency signals without any change compared with the typical MAF. This means that the phase-lead compensator actually amplifies the frequency signal f≠100n (n=1, 2, 3, …), which decreases the frequency adaptive of the MPLC-PLL under harmonics in off-nominal frequency scenarios.

Fig. 9.Bode diagram of the MAF and the cascade connection of MAF and phase-lead compensator.

E. DMAF-PLL

Fig. 10 shows the general structure of the DMAF-PLL.

Fig. 10.Block diagram of the DMAF-PLL proposed in [36].

The ‘DP’ represents the decoupling transfer function. The expressions of vα and vβ are shown in (13). Fig. 11 shows the block diagram of the PLL structure used in the experiment, where one additional MAF (hereafter called aMAF) is added before the DMAF-PLL. Therefore, the DMAF-PLL input signal is free of dc offset.

Fig.11.Block diagram of DMAF-PLL used in the experiment.

In [36], the aMAF block is designed to be frequency-adaptive using the rounding-down method N=round (mπ/ω0Ts), where m=2. Although this structure can effectively filter out the dc offset, the aMAF requires a time interval of 0.02 s to reach the steady-state condition. In Fig. 10, the transfer functions of DIFd and DIFq are:

Since vq has a 90° phase lag compared with vd, it can be obtained that vd/vqj. Thus, substituting s=jω into (18) and performing a simple mathematical operation [36], it is possible to get:

Substituting ω=-2ωn into (19), the value of DP becomes zero, which implies that the DP eliminates the negative sequence 2nd order harmonics. Therefore, from (4), can be expressed as:

From (20), the lowest order harmonics that needs to be blocked is the 6th order harmonic. Then, Tω is reduced to 1/300 s from 0.01 s, which significantly improves the response speed.

The small signal model of the DMAF-PLL is shown in Fig. 11. The decoupling transfer function DP in the z-domain can be denoted as:

Therefore, the open-loop transfer function of the DMAF-PLL in the z-domain can be written as:

It should be noted that the window length Tω in the MAF is calculated as 1/300, which results in approximately N=33.

Fig. 12.Small-signal model of the DMAF-PLL [36].

Thus, when the grid voltages are contaminated by harmonics, a small ripple may exist in the estimated frequency and phase angle.

 

III. PARAMETERS DESIGN GUIDELINES

In this Section, the control parameters design method of the MAF-based PLL is presented. Then, the frequency domain analysis of the PLL algorithms is outlined.

In order to simplify the parameters design procedure, the parameters kp and ki are designed in the s-domain. Then a discrete model and z-domain bode diagrams are used to test and adjust the control parameters. Therefore, the stability and disturbance rejection capabilities of the PLLs are ensured. The expression of the MAF is approximated by a LPF, as shown in (1), and the PI regulator is denoted as kp+ki/s. Thus, for the QT1-PLL, the open-loop transfer function can be derived as:

From (23), the proportional gain kp is the only parameter that needs to be designed in the QT1-PLL and HPLL, since the MAF window lengths have already been selected. Hence, the closed- loop transfer function can be derived as:

By comparing to the standard second order system, it is possible to obtain:

where ξ is the damping factor, and is the natural frequency.

Substituting Tω=0.01 s and ξ=0.707 into (25), yields kp≈100. The next step is to adjust kp on the basis of the real transfer function in the z-domain, as shown in (10) and (15). Since the value of kφ in (15) is small, the expressions (10) and (15) are almost identical.

Thus, the phase margin (PM), crossover frequency (CF), and gain margin (GM) of (10) as functions of kp are derived, as shown in Fig. 13. It can be seen that when kp varies from 50 to 150, the PM (blue line) varies from 56.7° to 34.2°, and the GM (red line) varies from 35.9 dB to 21.9 dB, which is suitable to ensure a sufficient stability margin. The CF (green line) shows a relatively smooth change (from 31.2 Hz to 35.5 Hz), which is much higher than the conventional PLLs, and a fast dynamic response can be guaranteed. Therefore, kp=92 is selected for the QT1-PLL and kp=94 is selected for the HPLL.

Fig. 13.The PM, CF, and GM of (5) as a function of kp in z-domain.

As for the MPLC-PLL, a cascade connection of the MAF and a phase-lead compensator provides a gain that is close to unity with a near zero phase shift in a low frequency range [35]. Therefore, the transfer function (17) can be approximated by a typical type-2 system. It can be obtained that:

In (26), by selecting ξ=0.707 and kp and ki can be calculated.

For the DMAF-PLL, the DP is ignored at first. When the MAF is replaced by a LPF, the standard design procedure presented in [38] can be applied to design the parameters of the DMAF-PLL. Therefore, the transfer function of the DMAF-PLL is derived as:

According to the symmetrical optimum method, kp and ki can be expressed as:

where ωc is the cutoff angle-frequency, and b is a constant which should be 2.4 [37]. In [36], Tω=0.0033 s, and ωc is set to 250 rad/s. Therefore, kp and ki can be calculated. According to the aforementioned parameters design method, the control parameters of the four MAF-based PLL algorithms are summarized in Table I.

TABLE IPARAMETERS OF THE MAF-BASED PLL ALGORITHMS

A bode diagram of the QT1-PLL, HPLL, MPLC-PLL, and DMAF-PLL is obtained by using the open-loop transfer functions of (10), (15), (17), and (22), as shown in Fig. 14. It can be noticed from Fig. 14 that the QT1-PLL (blue solid line) and the HPLL (green dot line) show almost the same frequency response, because the difference between QT1-PLL and the HPLL lies mainly in coordinate transformation instead of the control loop. The crossover frequencies (CFs) of the QT1-PLL and the HPLL are both 32.9 Hz, which ensures a relatively fast dynamic response. The GM and PM are 27.6 dB and 45.5°, respectively, which ensures a sufficient stability margin of these PLLs.

Fig. 14.Bode diagram of open-loop transfer functions of the MAF-based PLLs.

The MPLC-PLL (red solid line) shows a similar frequency response compared with the QT1-PLL and HPLL. In addition, the CF of the MPLC-PLL is approximately 30.7 Hz, which is much higher compare with the conventional MAF-based PLL. The GM and PM are 20.4 dB and 55°, respectively, which is the desired stability margin. However, the DMAF-PLL shows a different frequency response compared with the other three PLL algorithms due to the difference between the MAF window lengths. The CF of the DMAF-PLL is the highest (about 62 Hz) due to its small window length and high proportional gain. In addition, the system GM and PM are 6.61 dB and 37.7°, respectively.

In the high frequency range, the four PLLs show similar amplitude-frequency characteristics. The DMAF-PLL algorithm almost blocks the high frequency components of the integer multiples of 300 Hz. However, for the other three PLLs, it is 100 Hz.

 

IV. SEQUENCE EXTRACTION METHODS

Fig. 15 shows a block diagram of the fundamental frequency positive (pos.) and negative (neg.) sequence amplitude extraction. The extraction method is shown in the dotted frame in which four input signals θ, vα, vβ, and ω0 are required. For the HPLL, it should be noticed that the phaseangle used for amplitude extraction is (not θ0). If θ0 is used, the input voltage should be (not vα, and vβ). However, this selection makes the extraction procedure sluggish. The signals mentioned in this section are all shown in the corresponding block diagram of each PLL. The transformation matrix to extract the positive and negative sequence is expressed as:

Fig. 15.Block diagram of the fundamental frequency positive and negative sequence amplitude extraction.

Thus, can be expressed as:

where f is the oscillating term caused by the unbalanced grid voltage, harmonics, and dc offset.

The MAF window length is set to be frequency adaptive (the estimated period is 2π/ω0). Therefore, the accuracy of the frequency estimation affects the accuracy of the positive and negative sequence components extraction to a large extent.

 

V. EXPERIMENTAL RESULTS AND DISCUSSIONS

The aim of this section is to evaluate the performances of the four PLLs under different grid voltage disturbance scenarios which are generated by a grid simulator using a three-phase voltage source inverter (VSI) controlled in the voltage control mode (VCM) [38]. To validate the analysis, an experimental prototype was built based on a 2.2 kW Danfoss inverter controlled in the VCM using a LCL output filter with a resistive load, where the capacitor voltage of the LCL filter was controlled to synthesize the virtual grid conditions. The inverter PWM frequency was set to 10 kHz in order to evaluate the PLL algorithms with a discrete time-step of 100 microseconds, as analyzed in this paper.

A dSPACE1006 platform was utilized to implement the Simulink-based control algorithms and the compiled executable file was downloaded to the dSPACE1006 controller to extract real-time grid-synchronization signals. The binary word size was only several kilobytes (kB) when the VCM was adopted for the inverter control and the four PLL algorithms were implemented, which facilities practical implementation in both fixed point and floating point digital signal processors (DSPs) [see Fig. 16] [39]. Detailed comparisons of the four PLL under different grid disturbance scenarios are shown in Table II and Table III.

Fig. 16.Photo of the experimental set-up [38, 39].

TABLE IINote: (a) and (b) represent setting time and frequency overshoot, respectively.

TABLE IIINote: (a) and (b) represent peak-to-peak frequency error and peak-to-peak phase error, respectively.

Case 1. Performance Comparison under 90° Phase-Angle Jumps

Fig. 17 shows the positive and negative sequence amplitudes, and Fig. 18 illustrates the estimated frequency and phase estimation error under phase-angle jumps of +90°. It can be noticed all of the PLLs can achieve zero steady-state error of the amplitude, frequency and phase in 2.5 cycles. However, the DMAF-PLL shows an overshoot of 60 Hz in the estimated frequency, and the HPLL shows the smallest overshoot (about 28 Hz). In terms of phase-angle estimation, the HPLL shows an overshoot of about 50°, and the MPLC-PLL shows the smallest overshoot (about 20°).

Fig. 17.Estimated pos. and neg. sequence amplitudes under +90° phase-angle jump.

Fig. 18.Estimated frequency and phase error under +90° phase-angle jump.

Case 2. Performance Comparison under +5 Hz Frequency Jumps

Fig. 19 shows the positive and negative sequence amplitudes under frequency jumps of +5 Hz. It can be seen that all of the PLLs can achieve zero steady-state error in the positive sequence except for the HPLL, where the steady-state error is caused by the non-frequency adaptive DSC. In the negative sequence frame, all of the PLLs can achieve zero steady-state error in about 3 cycles.

Fig. 19.Estimated pos. and neg. sequence amplitudes under frequency jump of +5 Hz.

Fig. 20 illustrates the estimated frequency and phase estimation error under frequency jumps of +5 Hz. Similar results are achieved for the four PLLs and the estimated frequency is locked to the rated value in about 2 cycles. The HPLL and the DMAF-PLL show similar overshoots of about 2.5 Hz. In terms of phase-angle estimation, the HPLL has the largest overshoot (12°), and other three PLLs show an overshoot of about 8°.

Fig. 20.Estimated frequency and phase error under frequency jump of +5 Hz.

Case 3. Performance Comparison under DC Offset

Fig. 21 shows the positive and negative sequence amplitudes under dc offset. Due to the application of aMAF in the DMAF-PLL and DSC in the HPLL, the two PLLs can achieve zero steady state error in the positive and negative sequence amplitudes. However, for the QT1-PLL and the MPLC-PLL, noticeable fundamental frequency oscillations can be observed in the positive and negative sequence amplitudes. Fig. 22 illustrates the estimated frequency and the phase estimation error under dc offset. Because the MAF in the QT1-PLL and the MPLC-PLL cannot filter out the fundamental frequency oscillations caused by dc offset, the two PLLs show similar fluctuations both in the estimated frequency and the phase angle. For the HPLL, the estimated frequency is locked to the rated value in about one cycle. However, for the DMAF-PLL, a longer response time is needed (about 2 cycles) to achieve zero steady-state error due to the large window length of the aMAF.

Fig. 21.Estimated pos. and neg. sequence amplitudes under dc offset.

Fig. 22.Estimated frequency and phase error under dc offset.

Case 4. Performance Comparison under a 0.4 p.u. Single-Phase Voltage Sag

Fig. 23 shows the positive and negative sequence amplitudes under a 0.4 p.u. single-phase voltage sag. It shows that all of the PLLs achieve zero steady-state error in both the positive and negative sequence amplitudes, which shows the fastest dynamic response. However, the DMAF-PLL algorithm shows the slowest transient response due to the use of aMAF.

Fig. 23.Estimated pos. and neg. sequence amplitudes under single-phase voltage sag.

Fig. 24 illustrates the estimated frequency and phase estimation error under a 0.4 p.u. single-phase voltage sag. It can be seen that the QT1-PLL shows the shortest response time (less than one cycle). However, for the DMAF-PLL, the response time is greater than 2 cycles. For the HPLL and the MPLC-PLL, the setting time is about 2 cycles. Similar transient overshoots in the frequency can be observed in the QT1-PLL, the DMAF-PLL and the MPLC-PLL (about 3 Hz), while the HPLL shows a frequency overshoot of about 1.8 Hz.

Fig. 24.Estimated frequency and phase error under single-phase voltage sag.

Case 5. Performance Comparison under a 0.4 p.u. Two-Phase Voltage Sag

Fig. 25 shows the estimated positive and negative sequence amplitudes, and Fig. 26 illustrates the estimated frequency and the phase estimation error under a 0.4 p.u. two-phase voltage sag. Similar to the case of a single-phase voltage sag, all of the PLLs can achieve zero steady-state error in the positive and negative sequence amplitudes, frequency and phase, and the QT1-PLL and the DMAF-PLL show the fastest and slowest dynamic responses, respectively. The highest and lowest overshoot in frequency is found in the MPLC-PLL (about 3.5 Hz) and the HPLL (about 1.5 Hz), respectively.

Fig. 25.Estimated pos. and neg. sequence amplitudes under two-phase voltage sag.

Fig. 26.Estimated frequency and phase error under two-phase voltage sag.

Case 6. Performance Comparison under a 0.4 p.u. Three-Phase Voltage Sag

Fig. 27 shows the positive and negative sequence amplitudes, and Fig. 28 illustrates the estimated frequency and the phase estimation error under a 0.4 p.u. three-phase voltage sag. In the positive and negative sequence amplitudes, the experimental waveforms are similar to the cases of single-phase and two-phase voltage sags. The estimated frequencies and phase errors of the QT1-PLL, the MPLC-PLL and the HPLL are not affected by three-phase voltage sags. However, a high overshoot of about 6 Hz in the estimated frequency and a slow dynamic response of about 3 cycles is found in the DMAF-PLL, which is mainly due to the highly nonlinear system caused by the aMAF.

Fig. 27.Estimated pos. and neg. sequence amplitudes under three-phase voltage sag.

Fig. 28.Estimated frequency and phase error under three-phase voltage sag.

Case 7. Performance Comparison under Voltage Flickers

Fig. 29 shows the positive and negative sequence amplitudes under voltage flickers. It can be observed that all of the PLLs fail to achieve zero steady-state error and an obvious ripple is found in both the positive and negative sequence amplitude.

Fig. 29.Estimated pos. and neg. sequence amplitudes under voltage flicker.

Fig. 30 illustrates the estimated frequency and the phase estimation error under voltage flickers. Similar to the case of a three-phase voltage sag, all of the PLLs are not affected by the voltage flicker except for the DMAF-PLL, which shows steady-state oscillations both in the estimated frequency (about 1.5 Hz) and in the estimated phase angle (about 3.5°), which may also be caused by the aMAF.

Fig. 30.Estimated frequency and phase error under voltage flicker.

Case 8. Performance Comparison under Noise Contaminations

To evaluate the noise immunity of the PLLs, a zero-mean Gauss white noise with a variance of σ2=0.01 is added to the input. The signal-to-noise-ratio (SNR) is 10 log (1/2σ2) =17 dB. The noisy waveform is sampled at a rate of 100 kHz, and is then fed to a digital anti-aliasing filter. This high sampling rate is used to avoid the aliasing effects and to increase accuracy. A digital first-order LPF with a cutoff frequency of 4 kHz is considered as an anti-aliasing filter. The output of the anti-aliasing filter is down sampled to 10 kHz and is fed to the PLL.

Fig. 31 shows the positive and negative sequence amplitudes, and Fig. 32 illustrates the estimated frequency and phase estimation errors. It can be seen that all of the PLLs have similar peak to peak steady-state oscillations, for the estimated positive and negative sequence amplitude. They are about 0.005 p.u. and 0.04 p.u., respectively, for the estimated frequency and phase, which are about 2 Hz and 0.4°, respectively.

Fig. 31.Estimated pos. and neg. sequence amplitudes under noise contaminations.

Fig. 32.Estimated frequency and phase error under noise contamination.

Case 9. Performance Comparison under Harmonics with a Frequency Jump

In order to analyze the frequency-adaptive performances of the four MAF-based PLLs, the harmonics (0.1 p.u. of the -5th, and 0.05 p.u. of the +7th, -11th, and +13th harmonics) with the frequency jump (+5 Hz) scenario are subjected to the grid voltage.

Fig. 33 shows the estimated positive and negative sequence amplitudes, and Fig. 34 illustrates the estimated frequency and phase estimation error. It can be seen that when the grid voltage only suffers from harmonics (before 0.2s), the four MAF-based PLLs can all achieve zero steady-state error in the amplitude, frequency and phase estimation. When a frequency jump occurs (0.2s), the DMAF-PLL shows the best steady-state performance with the lowest oscillation. However, the MPLC-PLL shows the biggest oscillation in the estimated frequency mainly because of the phase-lead compensator which actually amplifies the error signal under harmonics with the off-nominal frequency condition. The detail steady-state oscillation amplitude is shown in Table III.

Fig. 33.Estimated pos. and neg. sequence amplitudes under harmonic with frequency jump.

Fig. 34.Estimated frequency and phase error under harmonic with frequency jump.

 

VI. PERFORMANCE IMPROVEMENT OF THE HPLL USING AMPLITUDE ERROR COMPENSATION METHOD

From the above performance comparison, it can be seen that all four of the PLL have satisfactory performance under various disturbances. For the HPLL, when a frequency jump occurs, an improvement method should be made to eliminate the steady-state error in the positive sequence amplitude estimation since extraction of the positive sequence of fundamental components is critical for the grid-connected inverters in grid synchronization. Therefore, inspired by the phase-error compensation (PEC) in the HPLL, the amplitude error compensation (AEC) is proposed herein. From (12), the αβDSC2 output signal amplitude can be written as:

Thus, the amplitude error caused by the αβDSC2 operator can be expressed as:

Since the average value of Δωo is equal to Δωi under the locked condition, the amplitude error at the output of the HPLL can be compensated by the online calculation of (33). A block diagram of the HPLL with AEC is shown in Fig. 35. indicates the positive sequence amplitude after the AEC and ka=T/4. It should be noted that the AEC is not connected to the control loop and that the dynamics of the HPLL are unaffected.

Fig. 35.Block diagram of HPLL with the proposed AEC.

Therefore, from Fig. 35, can be expressed as:

Experimental result with and without the AEC is shown in Fig. 36. This shows that the AEC effectively compensates the amplitude error and achieves zero steady-state error in about 1.5 cycles.

Fig. 36.Estimated positive sequence amplitude with and/or without AEC under frequency jump of +5 Hz.

 

VII. CONCLUSION

In this paper, a detailed analysis and performance comparison of four MAF-based PLLs is presented. For the QT1-PLL, the introduction of the quasi-type-1 control structure effectively improves the dynamic response of the MAF-PLL. The lack of dc offset and even order harmonic rejection is the main disadvantages of this PLL algorithm. Apart from this, the QT1-PLL shows satisfactory steady-state and dynamic performance, and disturbance rejection capability under other grid voltage disturbance conditions.

The HPLL can be perceived as an improved version of the QT1-PLL algorithm. The application of the αβDSC2 block can effectively overcome the shortcomings of the QT1-PLL without jeopardizing its dynamic performance and filtering capability. However, the disturbance rejection capabilities of the HPLL and the QT1-PLL decrease with frequency deviations from their nominal values under a harmonic scenario caused by the non-frequency adaptive MAF and DSC. Then an associated drawback of the HPLL is the amplitude tracking error [see Fig. 19]. To tackle this problem, the amplitude error compensation (AEC) method is proposed in the last section. This method effectively compensates the amplitude error and ensures the accuracy of the positive sequence component extraction.

For the MPLC-PLL, cascading of the MAF and the phaselead compensator results in a fast dynamic response of the SRF-PLL and improved disturbance rejection capability of the MAF-PLL while increasing the frequency estimation error under harmonics with the off-nominal frequency scenario. However, like the QT1-PLL the MPLC-PLL is also not suitable for grid-synchronization when the grid voltages contains dc offset and even order harmonics. Under other grid voltage disturbance scenarios, the MPLC-PLL can be a good choice.

For the DMAF-PLL, the window length of the MAF in the control loop is drastically reduced through the use of ‘DP’ which significantly improves the system dynamic response. The frequency adaptive aMAF (n=2 as shown in Section II Part A) ensures the best steady-state performance under harmonics with the off-nominal frequency scenario. However, it has the disadvantage of making the dynamic response sluggish and may even lead to system instability under some circumstances like voltage sag and flicker. Hence, it can be concluded that the DMAF-PLL can be used for grid-synchronization when the grid voltage is free from sag and flicker. The research findings of this paper may serve as a useful guideline for the grid-synchronization of three-phase grid-connected PWM inverters and distributed generators (DGs) in smart grids.