IGBT Open-Circuit Fault Diagnosis for 3-Phase 4-Wire 3-Level Active Power Filters based on Voltage Error Correlation

Abstract

A novel open-circuit fault diagnosis method for 3-phase 4-wire 3-level active power filters based on voltage error correlation is proposed in this paper. This method is based on observing the output pole voltage error of the active power filter through two kinds of algorithms. One algorithm is a voltage error analytical algorithm, which derives four output voltage error analytic expressions through the pulse state, current value and dc bus voltage, respectively, assuming that all of the IGBTs of a certain phase come to an OC fault. The other algorithm is a current circuit equation algorithm, which calculates the real-time output voltage error through basic circuit theory. A correlation is introduced to measure the similarity of the output voltage errors between the two algorithms, and OC faults are located by the maximum of the correlations. A FPGA has been chosen to implement the proposed method due to its fast prototyping. Simulation and experimental results are presented to show the performance of the proposed OC fault diagnosis method.

I. INTRODUCTION

The active power filter (APF) has been widely used for harmonic compensation in industrial areas. The principle of active filtering was established decades ago in [1]. The APF can be treated as a special controlled converter, which shares the same topologies as the H bridge, 2-level, NPC 3-level, etc. Since IGBTs and other semiconductors play a crucial role in these converters, their failures can greatly interrupt or even damage a system, which can result in security problems and economic losses.

According to [2], nearly 40% of the failures in power devices are semiconductor and soldering failures. Therefore, reliability is always a focus in [3]. For the IGBT itself, short-circuit (SC) and open-circuit (OC) faults are the two most common faults, where SC faults are usually destructive and result in a direct shut down of the system. Advanced IGBT drivers are usually designed with SC protection, where a system controller can detect the protection signal and turn off all of the pulses within several μs. When compared to SC faults, OC faults have a higher rate and are more likely to go undetected.

During the past 4 decades, multilevel converters have been under research and development in terms of successful industrial applications, as mentioned in [4], [5]. Multilevel converters increase the number of the output voltage values, leading to low harmonics of the output voltage. A comparison of the common topologies for 3-level converters versus 2-level converters is discussed in [6], which shows the great advantages of multilevel converters. For APFs, the multilevel topology is also widely used to increase the capacity and to obtain a better compensation performance. However, multilevel topology result in an increased number of IGBTs, which increases the probability of IGBT failure.

Research has been carried out on both the OC fault diagnosis and fault tolerance of power converters. For OC fault diagnosis, this research is mainly focused on converters [7]-[11], motor drive systems [12]-[17] and DC/DC converters [18], when compared to the much more reduced work on active power filters. In addition, many methods have been proposed for 2-level converters [13]-[17]. However there have only been a few for 3-level converters [7]-[12].

Current-based and voltage-based methods are common OC fault diagnosis strategies. In terms of the current-based proposals in the literature, the current Park’s Vector method has been proposed as a fault diagnostic tool for 2-level converters [19], [20]. However, it requires very complex pattern recognition algorithms, which are not suitable for integration into drive controllers. Despite this fact, many fault diagnostic methods are based on this first strategy. The average current Park’s Vector method was introduced in [21]. Further works based on the analysis of the current space vector trajectory diameter were proposed in [22], [23]. The major drawbacks of these proposals are their load dependence and sensitivity to transients, which result in unsatisfactory performance for low load conditions and false alarms during transients. To overcome these weaknesses and to enhance the robustness, a normalized average currents method was proposed in [24] and the absolute values of the normalized average currents are considered in [25]. A combined method based on both the derivative of the current Park’s vector phase and the current polarity was proposed in [26]. It possesses an excellent immunity to false alarms.

On the other hand, voltage-based methods have a faster response than current-based methods [27], [28]. However, they usually need additional detection hardware, which increases the drive costs and complexity. A direct comparison between the measured voltages and the reference values was proposed in [29] and a time delay was introduced to prevent false alarms. A FPGA based fault location approach was introduced in [30], with detection times shorter than 10 μs. Alternatively, a low-cost proposal based on indirect voltage measurement was obtained using high-speed photocouplers in [31]. However, well-defined time delays dependent on the nature of the power converter are still required.

In summary, current-based methods are independent of system parameters and no additional sensors are needed. Voltage-based methods rely on extra hardware, but they possess a fast detection time. Furthermore, some well-defined time-delay values must be correctly defined to avoid false alarms.

In addition, some other methods, such as wave-let fuzzy algorithm [32], wavelet-neural network [33] and rule-based expert systems [34] can be chosen for OC fault diagnosis. For these methods, 3-phase currents, inverter pole voltage, phase voltage, switch voltages, DC link current or user input are all potential quantities which can be chosen as detection parameters. For expert systems, user input can use a combination of the above parameters.

Most of the fault diagnosis proposals in the literature are designed for rectifiers, motor drive systems or DC/DC converters. As in APF systems, the load situation becomes more complicated and changeable, and the requirements for the fault diagnosis method are increased.

Generally, APF OC fault diagnosis is more difficult than rectifiers and motor drive systems due to the following reasons:

As a result, the previous current Park’s Vector method and the average Park’s Vector method could fail for APFs.

Limited work has been done on APF OC fault diagnosis and tolerance. An OC fault diagnosis method based on classical voltage measurements and combinatory logic was proposed in [35]. A similar method was given in [36], with current sensor fault consideration. [35] and [36] both proposed 2-level APFs with additional sensors.

An APF OC fault diagnosis and tolerance method based on a NPC 3-level was proposed in [37]. This method is based on a direct comparison between estimated filter line voltages and the expected voltages without additional sensors. However, the calculation precision cannot be guaranteed and no experimental results are given in [37].

In [38], an advanced strategy was proposed for APF OC fault diagnosis through an analysis of converter voltage errors and conditions under which large errors occur. The voltage error calculation precision is improved by consideration of near-zero current situations, which has an influence on the voltage error values. Additionally, the diagnostic time is reduced in some situations and no additional sensor is required. The same method was used in NPC 3-level rectifier OC fault diagnosis in [39]. Both [38] and [39] are based on the dSpace platform.

In [37]-[39], the voltage error was estimated by using circuit equations, where di/dt must be involved. In a discrete digital control system, di/dt is calculated by using the last period value i(k-1)(k=1,2,3…) and TS, which means that a TS time delay constantly exists. As a result, the estimated voltage will never be exactly the same as the real voltage. The error can be reduced by a higher sampling frequency, but it cannot be eliminated. This has a direct influence on the OC fault diagnosis, which was not considered in [37]-[39].

In this paper, a novel OC fault diagnosis method for 3-phase 4-wire 3-level active power filters based on voltage error correlation is proposed. For ground neutral systems, the APF should have a compensation ability for the neutral wire current and a 4-wire compensation system is needed [40]. Therefore, the OC fault diagnosis becomes more complicated. No published work has discussed 3-level 4-wire APF OC fault diagnosis.

The given method is based on [38]. However, its reliability is greatly improved. The zero current situation is considered and no additional sensors are required. Instead of judging an OC fault solely by the amplitude of the calculated pole voltage error, which can be affected by the sampling frequency and the sampling accuracy, a more reliable algorithm is proposed. A Butterworth filter strategy is introduced to eliminate the noise of the pole voltages, obtained through the two given methods, and the correlation is compared during a supply period. A FPGA is chosen to implement the given method and the OC faults are located within 40.1ms.

The main advantages of the proposed pole voltage error correlation-based approach are as follows:

However, there are some drawbacks to the proposed method. The algorithm must be implemented on a very fast digital target, such as a FPGA or a CPLD, which increases the hardware costs. Although no additional sensors are demanded, ADCs with a very high frequency bandwidth are required. This algorithm needs a large amount of calculation, which increases the burden on the controller. In addition, the response time of the proposed algorithm is between 20.1ms~40.1ms, which is longer than the conventional voltage-based method.

The given algorithm is explained in Section II. In addition, experimental results and FPGA implementation will be presented in Section III. Some conclusions are presented in Section IV.

 

II. OPEN-CIRCUIT FAULT DIAGNOSIS ALGORITHM

A. System under Healthy Conditions

The 3-phase 4-wire 3-level NPC APF topology is represented in Fig.1. For each leg (A or B or C), there are 4 IGBTs and 6 Diodes, which are defined as SX1, SX2, SX3, SX4, DX1, DX2, DX3, DX4, D1 and D2. In this paper, X∈(A, B, C). The output current iX of leg X is shown in Fig. 1, with a reference direction.

Fig. 1.Schematic of the 3-line 4-wire APF.

VXM is defined as the output pole voltage between point X and point M under healthy conditions. For the NPC 3-level topology, the pulse state SX={1,0,-1} is introduced to each leg. When SX=1, SX1 and SX2 turn on, and point X is connected to the dc bus “+” through SX1 and SX2(iX>0) or DX1 and DX2(iX<0). When SX=0, SX2 and SX3 turn on, and X point is connected to point M through D1 and SX2(iX>0) or SX3 and D2(iX<0). When SX=-1, SX3 and SX4 turn on, and point X is connected to the dc bus “-” through DX4 and DX3(iX>0) or SX3 and SX4(iX<0).

The pole voltage VXM in healthy conditions is given by:

B. Voltage Error Analytical Algorithm

is defined as the output pole voltage between point X and point M under fault conditions. The value of differs when an OC fault of SX1, SX2, SX3 or SX4 occurs, which will be discussed later.

When SX1 comes to open fault, if the pulse state SX=0 or -1, SX1 is kept off. If SX=1 and iX<0, current flows to the dc bus “+” through DX1 and DX2, and is not affected. If SX=1 and iX>0, point X is cut off from the dc bus “+” and finds a new current path of M->D1->SX2->X. In this case,

When SX2 comes to an OC fault, if the pulse state SX=-1, SX2 is kept off. If SX=0 and iX<0, current flows to point M through SX3 and D2, and is not affected. If SX=0 and iX>0, point X is cut off from point M, and current flows following the path of “-”->DX4->DX3->X. In this case, If SX=1 and iX<0, current flows to point M through DX1 and DX2, and which is equal to VXM under healthy conditions. If SX=1 and iX>0, current flows following the path of “-”->DX4->DX3->X, and

Similarly, the situations of SX3 and SX4 OC faults can be analyzed. Thus, the output pole voltage differs in terms of fault conditions, as shown in Table I.

TABLE ITHE VALUES OF AND VXM IN OC FAULT CONDITIONS

From what has been discussed above, no matter which IGBT comes to an OC fault, the current can find a new path and point X can connect to point M, dc bus “+” or dc bus “-”. However, in real situations, if the current iX falls below the holding current, the IGBT is turned off. This means than when iX=0 or iX≈0 happens, as shown in Fig. 2, is not simply equal to udc1, 0 or -udc2. in the iX=0 or iX≈0 conditions will be derived later.

Fig. 2.The value of conditions.

The equivalent circuit in the iA=0 or iA≈0 condition is shown in Fig. 3.

Fig. 3.The equivalent circuit in iA=0 or iA≈0 conditions.

Fig. 3 can be described through the following equations:

Approximately, iB+iC+iN≈0. Assuming that LA=LB=LC=LN, then According to (2), (3) and (4), the output pole voltage is given by:

Similarly:

To sum up, is defined as the real output pole voltage between point X and point M under fault conditions, which is given by:

Where ε is a small value and ε>0.

Then:

When an OC fault occurs, the output pole voltage differs from that under healthy conditions. The output pole voltage error can be calculated by (9). This method is called voltage error analytical algorithm. Matlab/Simulink is used to verify the performance of this algorithm under different power conditions. A rectifier load, an inductive load and a capacitive load are considered as 3 typical load conditions, which are shown in Fig. 4. The simulation parameters are shown in Table II.

Fig.4.Various loads of simulation.

TABLE IISIMULATION PARAMETERS

Simulation results of a SA1, SA2 OC fault are shown in Fig. 5, Fig. 6 and Fig. 7, where Fig. 5 represents a rectifier load,

Fig. 5.Comparison between measured output pole voltage error and by voltage error analytical algorithm when SA1 OC fault (a) and SA2 OC fault (b) with rectifier load.

Fig. 6.Comparison between measured output pole voltage error and by voltage error analytical algorithm when SA1 OC fault (a) and SA2 OC fault (b) with inductive load.

Fig. 7.Comparison between measured output pole voltage error and by voltage error analytical algorithm when SA1 OC fault (a) and SA2 OC fault (b) with capacitive load.

Fig. 6 represents an inductive load, and Fig. 7 represents a capacitive load. Comparisons between and the actual measured output pole voltage error are illustrated in small windows for all 3 different power conditions. The calculated and the actual voltage error match each other well, which shows the accuracy of voltage error analytical algorithm. In Fig. 5, Fig. 6 and Fig. 7, (i=1,2,3 or 4) stands for in a SXi OC fault.

It can be seen from Fig. 5, Fig. 6 and Fig. 7 that the given voltage error analytical algorithm is not affected by the type of load, and can accurately calculate the output pole voltage error under a variety of load conditions.

The voltage error analytical algorithm is easy to implement without additional sensors, since eX, iX, udc1 and udc2 are required for APF control systems and the pulse state SX is ready to use (e.g. in FPGA or CPLD).

However, (9) will not come to alive until an OC fault moment arrives. That is to say (9) is incorrect under healthy conditions. Thus, is defined before an OC fault moment.

C. Current Circuit Equation Algorithm

The authors of [38] proposed a method for estimating the output pole voltage by a circuit equation. To avoid common mode voltage, line-to-line voltage is used to perform an indirect analysis of the pole voltage error. As in a 3-phase 4-wire system, point M is connected to point N, no common mode voltage is involved and the output pole voltage can be derived similarly by a circuit equation.

is defined as the output pole voltage between point X and point M, which is obtained by a current circuit equation algorithm. An equivalent circuit is shown in Fig. 8.

Fig. 8.Equivalent circuit of phase X.

The equation is given by:

In a discrete digital control system, the current rate is given by:

Where k=1,2,3⋯; TS is the sampling time.

Thus, the output pole voltage is given by:

As discussed previously, (9) is only correct when an OC fault occurs. By comparison, (12) is correct in both healthy and fault conditions, which is its major advantage. However, for actual discrete digital systems, the calculation accuracy of is severely influenced by the sampling frequency. As in (11), iX(k-1) is used to calculate the current rate diX/dt, where a TS period delay exists. The calculation error cannot be eliminated even if TS is reduced to the μs level. Fig. 9 illustrates a comparison between and the measured pole voltage error, with a sampling frequency of fS=1/TS=80kHz and a switching frequency of fswitch=10kHz.

Fig. 9.Comparison between and measured output pole voltage.

Therefore, by (12) contains narrow pluses near fswitch, which has a major influence on the OC fault location. [38] locates an OC fault according to the amplitude of However, how the limitation of fS affects the result of the fault location is not discussed.

D. Noise Elimination Strategy

Two methods, a voltage error analytical algorithm and a current circuit equation algorithm have been introduced above to calculate the output pole voltage.

In ideal situations, there is

However, is full of noise around the sampling frequency, which interferes with effective OC fault information. To clearly illustrate this problem, simulation waveforms of (a SA1 OC fault, for example) with a rectifier load are shown in Fig. 10, while fS=1/TS=80kHz and fswitch=10kHz.

Fig. 10.Waveforms of of SA1 OC fault with rectifier load.

As shown in Fig. 10, (13) fails under both the healthy and fault conditions. In order to use as an OC fault diagnostic reference, a second-order Butterworth filter noise elimination strategy is proposed. Butterworth demonstrated a low pass filter whose frequency response (gain) is:

where ωcut-off=2πfcut-off is the angular frequency in radians per second. If ω/ωcut-off=1, the amplitude response of this filter in the passband is If ω/ωcut-off>1, the response slopes off linearly toward negative infinity at -40dB per decade.

In this paper, fcut-off is set to 2kHz, which is less than fswitch. under healthy conditions (i.e. t<0.2s in Fig. 10), is brought into the designed second-order Butterworth filter and the frequency spectrum of the filter input and output are shown in Fig. 11, where the high frequency component gain is significantly attenuated as a result.

Fig. 11.Frequency spectrum of before and after designed second-order Butterworth filter.

Then, of a SA1 OC fault with a rectifier load, shown in Fig. 10, are both brought into Butterworth filters and turn into what is shown in Fig. 12(a), where are defined as the output of the Butterworth filters, and Similarly, simulation results of SA2, SA3 and SA4 OC faults with a rectifier load are shown in Fig. 12(b)-(d), respectively. Here, the simulation parameters are the same as those shown in Fig. 4 and Table II.

Fig. 12.Filtered pole voltage error of Leg A by 2 proposed algorithms when: (a) SA1 OC fault, (b) SA2 OC fault, (c) SA3 OC fault and (d) SA4 OC fault with rectifier load.

For inductive and capacitive load conditions, the Butterworth filter also achieves a very good performance in noise elimination, which is shown in Fig. 13(a)-(d) and Fig. 14(a)-(d).

Fig. 13.Filtered pole voltage error of Leg A by 2 proposed algorithms when: (a) SA1 OC fault, (b) SA2 OC fault, (c) SA3 OC fault and (d) SA4 OC fault with inductive load.

Fig. 14.Filtered pole voltage error of Leg A by 2 proposed algorithms when: (a) SA1 OC fault, (b) SA2 OC fault, (c) SA3 OC fault and (d) SA4 OC fault with capacitive load.

As shown in Fig. 12, Fig. 13 and Fig. 14, match each other perfectly under various loads conditions. The calculation of the error voltage is independent of load changes. For inductive, capacitive and rectifier loads, this method has a high accuracy and adaptability. It is worth emphasizing that, during the filtering process, part of the effective fault information will be filtered too, resulting in an amplitude reduction of useful information. However, this does not affect the distinction between the fault waveforms.

As shown in Fig. 12, Fig. 13 and Fig. 14, under all of the IGBT OC faults are so different from each other that can be treated as a fault feature. When a certain IGBT comes to a fault, can be compared with respectively, and the fault can be located by its similarity.

E. OC Fault Diagnosis based on Voltage Error Correlation

Let v1 and v2 be random variables having finite means. Let E(v1) and E(v2) be expectations of v1 and v2, respectively. The covariance of v1 and v2, which is denoted by Cov(v1, v2), is defined as:

Then the correlation of v1 and v2, which is denoted by μ(v1, v2), is defined as follows:

(15) and (16) can be used to measure the association between two random variables v1 and v2, where (15) is normalized to “1” through (16).

The proposed OC fault diagnosis is implemented as follows: First, a pole voltage error of three phases is calculated through the current circuit equation algorithm and then filtered, where is obtained. Second, if of a certain phase is greater than λ(e.g., λ=0.5), then X phase is judged with an OC open fault. Third, once an OC open fault is confirmed, (9) comes to alive and are calculated through the voltage error analytical algorithm. Then are filtered, and are obtained. Fourth, assuming that μX1, μX2, μX3 and μX4 are calculated by (16). Finally, assuming that μXi is the maximum of μX1, μX2, μX3 and μX4 then SXi is an OC fault IGBT as the final diagnosis result. Furthermore, to prevent the occurrence of a misdiagnosis, μXi of the fault IGBT must be greater than a certain value (e.g., 0.7), or the diagnosis result will be abandoned. The proposed algorithm is shown in Fig. 15.

Fig. 15.Proposed OC fault diagnosis algorithm.

Simulation results for all twelve of the IGBTs with a rectifier load, an inductive load, and a capacitive load are shown in Table III, IV and V, with the simulation parameters in Fig. 4 and Table II. For various load conditions, the diagnostic accuracy is up to 100%. These results demonstrate the good performance of the proposed algorithm.

TABLE IIIMaximum μX of SXi open fault, and fault IGBT located here.

TABLE IVMaximum μX of SXi open fault, and fault IGBT located here.

TABLE VMaximum μX of SXi open fault, and fault IGBT located here.

 

III. EXPERIMENTAL RESULTS

A 3-phase 4-wire 3-level NPC prototype is developed to validate the proposed OC fault diagnosis algorithm, as shown in Fig. 16. A rectifier load, an inductive load and a capacitive load, as shown in Fig. 4, are all considered to verify the adaptability of the proposed method. The experimental parameters are the same as simulation parameters shown in Table II.

Fig. 16.Experimental prototype.

In the process of OC fault diagnosis, the pulse state is involved in calculation, which requires a high sampling frequency and a fast computing controller. Therefore, a control unit based on a FPGA+DSP is developed, in which the FPGA is mainly working on proposed algorithm and the DSP is for the APF double closed-loop control. The diagnosis part is shown in Fig. 17.

Fig. 17.FPGA implementation of proposed OC fault diagnosis algorithm.

The sampling frequency of an AD7606 (16 bits) is set to fs=80kHz(8 times the fswitch). Thus, are updated every 12.5μs (i.e. 80kHz). According to Shannon's sampling theorem, for a given sample rate fs, perfect reconstruction is guaranteed to be possible for a band-limit Bs < fs/2. Therefore, the discrete second-order Butterworth filter is designed with a sample time of 160kHz. The process of this filter is shown in Fig. 18. At least 480ns is needed for one variable filtering, which is far less than 6.25μs (i.e. 160kHz).

Fig. 18.Process of second-order Butterworth filter in FPGA.

To save the FPGA’s resources and to shorten the calculation time, only a period of 20ms is utilized for data saving, which begins at the moment of In addition, only 128 data of are saved into RAM to wait for correlation judgment. Here 128 data are obtained with a sampling time of 156.25μs during 20ms.

Experimental results with a rectifier load are shown in Fig. 19 and Fig. 20. Fig. 19 displays waveforms of SA1 OC faults, and Fig. 20 displays waveforms of SA2 OC faults. Table VI shows μX and the judgments for all twelve IGBT OC faults with the rectifier load condition.

Fig. 19.Waveforms of SA1 OC faults: (a) (b) and judging signal with rectifier load.

Fig. 20.Waveforms of SA2 OC faults: (a) (b) and judging signal with rectifier load.

TABLE VIMaximum μX of SXi open fault, and fault IGBT located here.

Experimental results with an inductive load are shown in Fig. 21 and Fig. 22. Fig. 21 displays waveforms of SA1 OC faults, and Fig. 22 displays waveforms of SA2 OC faults. Table VII shows μX and the judgments for all twelve IGBT OC faults with the inductive load condition.

Fig. 21.Waveforms of SA1 OC faults: (a) (b) and judging signal with inductive load.

Fig. 22.Waveforms of SA2 OC faults: (a) (b) and judging signal with inductive load.

TABLE VIIMaximum μX of SXi open fault, and fault IGBT located here.

Experimental results with an inductive load are shown in Fig. 23 and Fig. 24. Fig. 23 displays waveforms of SA1 OC faults, and Fig. 24 displays waveforms of SA2 OC faults. Table VIII shows μX and the judgments for all twelve IGBT OC faults with the capacitive load condition.

Fig. 23.Waveforms of SA1 OC faults: (a) (b) and judging signal with capacitive load.

Fig. 24.Waveforms of SA2 OC faults: (a) (b) and judging signal with capacitive load.

TABLE VIIIMaximum μX of SXi open fault, and fault IGBT located here.

In Table VI, VII and VIII, experimental results of the proposed algorithm are shown under various loads. All twelve IGBTs OC fault are successfully located with different power conditions, which shows the good performance of the proposed method.

The whole diagnosis response time costs tλ+20ms+tcal, as shown in Fig. 25. Here, 20ms refers to a whole supply period, during which the processes of relevant variable sampling, computing and storage are repeatedly done. tcal stands for the correlation calculation, which is mainly determined by the max clock frequency in the FPGA. For the 50MHz clock frequency condition, tcal has been tested at less than 100μs. tλ is defined as the time between the coming moment of an OC fault and the moment arrives. tλ is not a fixed value that is dependent on load changes and fault’s coming moment. Therefore, it is really hard to precisely calculate the value of tλ. However, it can be sure that will occur in the next 20ms of the OC coming moment and that tλ is definitely less than a supply period (20ms). tλ can be 0ms, which means that occurs right after the coming moment of an OC fault. On the other hand, the worst situation for tλ is illustrated in Fig. 25, where tλ=20ms. In conclusion, the diagnosis response time for the proposed algorithm is between 20.1 ms~40.1ms.

Fig. 25.Response time of the given OC fault algorithm.

 

IV. CONCLUSIONS

A novel open-circuit fault diagnosis method for 3-phase 4-wire 3-level active power filters based on voltage error correlation is proposed in this paper. The method is based on converter output pole voltage error observing. A comparison between the actual pole voltage error and the analytic expecting voltage error under fault conditions is implemented though a FPGA and a correlation is introduced to locate the OC fault IGBT. A Butterworth filter is considered to eliminate the noise caused by the discrete system accuracy limitation. The zero current condition is considered and no additional sensors are needed. In addition, high location accuracy is guaranteed through this method.

The proposed method is independent of various loads conditions, such as a rectifier load, an inductive load and a capacitive load. It has good performance under unbalanced load current situations and both effectiveness and reliability can be achieved.

There are some drawbacks to the given method. The proposed method must be implemented on a very fast digital target, such as a FPGA or a CPLD, which increases the hardware costs. In addition, ADCs with a very high frequency bandwidth are required.

The simulation and experimental results demonstrate the good performance of the algorithm. An OC fault can be located within 40.1ms. This response time is acceptable, since it is accompanied by a higher reliability and accuracy.