Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Loop Filter Voltage Variation Compensated PLL with Charge Pump

전하펌프를 이용한 루프 필터 전압변화 보상 위상고정루프

  • An, Seong-Jin (Department of Electronic Engineering, Pukyong National University) ;
  • Choi, Yong-shig (Department of Electronic Engineering, Pukyong National University)
  • Received : 2016.07.21
  • Accepted : 2016.08.10
  • Published : 2016.10.31
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Abstract

This paper proposes a phase-locked loop (PLL) to minimize the loop filter output voltage fluctuation by using a comparator including RC time constant circuits. The voltage variation of loop filter is inputted to RC time constant circuits which have two RC time constants, large and small. While a small RC time constant circuit quickly conveys the output voltage variation of loop filter, a large RC time constant circuit conveys slowly the output voltage variation of loop filter and its output looks like constant voltage. The output signal of the comparator controls the sub charge pump and reduces the input voltage variation of voltage-controlled oscillator (VCO). Therefore, the proposed PLL generates a phase noise reduced signal. It has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.

본 논문에서는 RC 시정수 회로를 포함하는 비교기를 이용해 보조 전하펌프를 제어하여 루프 필터 출력 전압 변동 폭을 최소화 하는 위상고정루프(PLL)를 제안하였다. 루프 필터의 출력 전압변화는 작은 시정수 값을 가지는 RC와 큰 시정수 값을 가지는 RC를 통해 비교기의 입력으로 각각 전달된다. 작은 시정수를 가지는 RC는 루프 필터의 신호의 변화를 빠르게 전달하는 반면 큰 시정수를 가지는 RC는 루프 필터의 신호를 매우 느리게 전달하여 일정한 크기의 전압과 같이 동작한다. 비교기의 출력 신호는 보조 전하펌프를 제어하고, 이는 전압제어발진기(VCO)의 입력 전압 변동 폭을 줄여준다. 그러므로 제안한 위상고정루프는 위상 잡음이 많이 제거된 신호를 생성한다. 제안된 위상고정 루프는 1.8V의 공급전압에서 0.18um CMOS 공정의 파라미터를 이용하여 Hspice로 시뮬레이션을 수행하고, 동작을 검증하였다.

Keywords

References

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