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Design and Implementation of Multi-channel FFT Processor for MIMO Systems

MIMO 시스템을 위한 다채널 FFT 프로세서의 설계 및 구현

  • Jung, Yongchul (School of Electronics and Information Engineering, Korea Aerospace University) ;
  • Cho, Jaechan (School of Electronics and Information Engineering, Korea Aerospace University) ;
  • Jung, Yunho (School of Electronics and Information Engineering, Korea Aerospace University)
  • 정용철 (한국항공대학교 항공전자정보공학부) ;
  • 조재찬 (한국항공대학교 항공전자정보공학부) ;
  • 정윤호 (한국항공대학교 항공전자정보공학부)
  • Received : 2017.10.23
  • Accepted : 2017.11.27
  • Published : 2017.12.31

Abstract

In this paper, a low complexity fast Fourier transform(FFT) processor is proposed for multiple input multiple output(MIMO) systems. The IEEE 802.11ac standard has been adopted along with the demand for a system capable of high channel capacity and Gbps transmission in order to utilize various multimedia services using a wireless LAN. The proposed scalable FFT processor can support the variable length of 64, 128, 256, and 512 for 8x8 antenna configuration as specified in IEEE 802.11ac standard with MIMO-OFDM scheme. By reducing the required number of non-trivial multipliers with mixed-radix(MR) and multipath delay commutator(MDC) architecture, the complexity of the proposed FFT processor was dramatically decreased. Implementation results show that the proposed FFT processor can reduced the logic gate count by 50%, compared with the radix-2 SDF FFT processor. Also, compared with the 8-channel MR-2/2/2/4/2/4/2 MDC processor and 8-channel MR-2/2/2/8/8 MDC processor, it is shown that the gate count is reduced by 18% and 17% respectively.

본 논문에서는 MIMO(multiple input multiple output) 시스템을 위한 저복잡도 FFT(fast Fourier transform) 프로세서의 설계 및 구현 결과를 제시하였다. 무선랜을 이용한 다양한 멀티미디어 서비스 등을 이용하기 위해 높은 채널 용량과 Gbps급 전송이 가능한 시스템에 대한 요구와 함께 IEEE 802.11ac 규격이 채택되었다. MIMO-OFDM (orthogonal frequency duplex multiplexing) 기술을 사용하는 IEEE 802.11ac 규격의 무선랜 시스템은 최대 8개의 안테나 구성 및 20-160 MHz 대역폭을 지원해야한다. 따라서, 제안된 FFT 프로세서는 8채널 64, 128, 256, 512 point 가변길이를 지원한다. 또한, 비단순 승산기의 수를 감소시키기 위해서 MRMDC(mixed-radix multipath delay commutator) 구조를 적용하였고, 이로 인해 제안된 FFT 프로세서는 기존 FFT 프로세서에 비해 현저히 낮은 복잡도로 구현 가능하다. 구현 결과, 제안된 FFT processor는 기존 방식인 radix-2 SDF 구조 대비 gate count가 50 % 감소 가능하였고, 8 채널 MR-2/2/2/4/2/4/2 MDC 구조와 8채널 MR-2/2/2/8/8 MDC 구조 대비 logic gate 수를 각각 18 %와 17 % 감소 가능함이 확인되었다.

Keywords

References

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