Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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A 2.496 Gb/s Reference-less Dual Loop Clock and Data Recovery Circuit for MIPI M-PHY

2.496Gb/s MIPI M-PHY를 위한 기준 클록이 없는 이중 루프 클록 데이터 복원 회로

  • Kim, Yeong-Woong (School of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Jang, Young-Chan (School of Electronic Engineering, Kumoh National Institute of Technology)
  • Received : 2016.12.22
  • Accepted : 2017.01.26
  • Published : 2017.05.31
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Abstract

This paper presents a reference-less dual loop clock and data recovery (CDR) circuit that supports a data rate of 2.496 Gb/s for the mobile industry processor interface (MIPI) M-PHY. An adaptive loop bandwidth scheme is used to implement the fast lock time maintaining a low time jitter. To this scheme, the proposed CDR consists of two loops for a frequency locked loop and a phase locked loop. The proposed 2.496 Gb/s reference-less dual loop CDR is designed using a 65 nm CMOS process with 1.2 V supply voltage. The simulated peak-to-peak jitter of output clock is 9.26 ps for the input data of 2.496 Gb/s pseudo-random binary sequence (PRBS) 15. The active area and power consumption of the implemented CDR are $470{\times}400{\mu}m^2$ and 6.49 mW, respectively.

본 논문은 2.496Gb/s 데이터 레이트를 갖는 mobile industry processor interface (MIPI) M-PHY를 위한 기준 클록이 없는 이중 루프 클록 데이터 복원 회로(CDR : Clock and Data Recovery Circuit)를 제안한다. 제안하는 클록 데이터 복원회로는 적응형 루프 대역폭 조절 기법을 사용하여 적은 타임 지터를 가지면서 빠른 고정 시간을 가질 수 있다. 클록 데이터 복원회로는 주파수 고정 루프와 위상 고정 루프로 이루어진다. 제안하는 2.496Gb/s 기준 클록이 없는 이중 루프 클록 데이터 복원 회로는 1.2V 공급 전압을 갖는 65nm CMOS 공정을 이용하여 설계되었다. 2.496Gb/s pseudo-random binary sequence (PRBS)15 입력에서 시뮬레이션 된 출력 클록의 타임 지터는 $9.26ps_{p-p}$이다. 클록 데이터 복원 회로의 면적과 전력 소모는 각각 $400{\times}470{\mu}m^2$와 6.49mW이다.

Keywords

References

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