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Efficient Hardware Design of Hash Processor Supporting SHA-3 and SHAKE256 Algorithms

SHA-3과 SHAKE256 알고리듬을 지원하는 해쉬 프로세서의 하드웨어 설계

  • Received : 2017.01.24
  • Accepted : 2017.02.21
  • Published : 2017.06.30

Abstract

This paper describes a design of hash processor which can execute new hash algorithm, SHA-3 and extendable-output function (XOF), SHAKE-256. The processor that consists of padder block, round-core block and output block maximizes its performance by using the block-level pipelining scheme. The padder block formats the variable-length input data into multiple blocks and then round block generates SHA-3 message digest or SHAKE256 result for multiple blocks using on-the-fly round constant generator. The output block finally transfers the result to host processor. The hash processor that is implemented with Xilinx Virtex-5 FPGA can operate up to 220-MHz clock frequency. The estimated maximum throughput is 5.28 Gbps(giga bits per second) for SHA3-512. Because the processor supports both SHA-3 hash algorithm and SHAKE256 algorithm, it can be applicable to cryptographic areas such as data integrity, key generation and random number generation.

본 논문에서는 새로운 해쉬 알고리듬인 SHA-3과 출력 길이 확장함수인 SHAKE256을 구현하는 해쉬 프로세서를 설계하였다. 해쉬 프로세서는 성능을 극대화하기 위해 Padder 블록, 라운드 코어 블록, 출력 블록이 블록 단계에서 파이프라인 구조로 동작한다. Padder 블록은 가변길이의 입력을 여러 개의 블록으로 만들고, 라운드 코어 블록은 on-the-fly 라운드 상수 생성기를 사용하여 SHA-3와 SHAKE256에 대응하는 해쉬 및 출력 확장 결과를 생성하며, 출력 블록은 결과 값을 호스트로 전달하는 기능을 수행한다. 해쉬 프로세서는 Xilinx Virtex-5 FPGA에서 최대 동작 속도는 220 MHz이며, SHA3-512의 경우 5.28 Gbps의 처리율을 갖는다. 프로세서는 SHA-3 와 SHAKE-256 알고리듬을 지원하므로 무결성, 키 생성, 난수 생성 등의 암호 분야에 응용이 가능하다.

Keywords

References

  1. W. Stalling, Cryptography and Network Security-Principle and Practices, 5th ed., Essex, England: Pearson, 2013.
  2. I. S. Janik, "High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs," Ms. D. dissertation, University of Windsor, Windsor, Ontario, Canada, 2015.
  3. X. Wang, Y. Yin, and H. Yu, "Finding collisions in the full SHA-1," in Advances in Cryptology(Crypto-2005) Lecture Notes in Computer Science, vol. 3621, Berlin, Heidelberg: Springer-Verlag, 2005, pp. 17-36.
  4. W. Stalling, "Inside SHA-3," IEEE Potentials, vol. 22, no. 6, pp. 26-31, Nov.-Dec. 2013.
  5. FIPS PUB 202, SHA-3 Standard: Permutation-Based Hash and Extendable-Output Functions, NIST, Gaithersburg, MD, Aug. 2015.
  6. B. Baldwin, A. Byrne, and L. Lu, "A Hardware Wrapper for the SHA-3 Hash Algorithms," in IET Irish Signals and Systems Conference, Cork, Ireland, pp.1-6, 2010.
  7. G. Provelengios et al, "FPGA-Based Design Approaches of Keccak Hash Function," in 15th Euromicro Conference on Digital System Design, Izmir, Turkey, pp.648-653, 2012.
  8. A. Arshad et al "Compact Implementation of SHA3-512 on FPGA," in 2014 Conference on Information Assurance and Cyber Security(CIACS), Rawalpindi, Pakistan, pp.29-33, 2014.
  9. S. Bayat-Sarma et al, "Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm," IEEE Transactions on CAD of Integrated Circuit and Systems, vol. 33, no. 7, pp.1105-1109, July 2014. https://doi.org/10.1109/TCAD.2014.2307002
  10. NIST, "SHA-3 example: Test vector," [Internet]. Available: http://csrc.nist.gov/groups/ST/hash/sha-3/fips202_standard_2015.html.
  11. K. K. Saluja, "Linear Feedback Shift Registers Theory and Applications," [Internet]. Available: http://homepages.cae.wisc.edu/-ece553/handouts/LFSR-notes.PDF.

Cited by

  1. SHA-3 해시 함수의 최적화된 하드웨어 구현 vol.22, pp.4, 2017, https://doi.org/10.7471/ikeee.2018.22.4.886