한국정보통신학회논문지 (Journal of the Korea Institute of Information and Communication Engineering)

  • 제21권8호
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  • Pages.1465-1470
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  • 2017
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  • 2234-4772(pISSN)
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  • 2288-4165(eISSN)
한국정보통신학회 (The Korea Institute of Information and Commucation Engineering)
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10 nm 이하 저도핑 DGMOSFET의 SPICE용 DIBL 모델

Drain Induced Barrier Lowering(DIBL) SPICE Model for Sub-10 nm Low Doped Double Gate MOSFET

  • Jung, Hakkee (Department of Electronic Engineering, Kunsan National University)
  • 투고 : 2017.04.03
  • 심사 : 2017.04.20
  • 발행 : 2017.08.31
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초록

기존의 MOSFET에서는 반전층보다 항상 실리콘 두께가 크기 때문에 드레인유도 장벽감소가 실리콘 두께에 관계없이 산화막 두께 및 채널길이의 함수로 표현되었다. 그러나 10 nm 이하 저도핑 이중게이트 구조에서는 실리콘 두께 전체가 공핍층이 형성되기 때문에 기존의 SPICE 모델을 사용할 수 없게 되었다. 그러므로 이중게이트 MOSFET에 대한 새로운 SPICE 용 드레인유도 장벽감소 모델을 제시하고자 한다. 이를 분석하기 위하여 전위분포와 WKB 근사를 이용하여 열방사 및 터널링 전류를 구하였다. 결과적으로 드레인유도 장벽감소는 상하단 산화막 두께의 합 그리고 실리콘 두께의 2승에 비례하며 채널길이의 3승에 반비례한다는 것을 알 수 있었다. 특히 SPICE 파라미터인 정적 궤환계수가 1과 2사이에서 사용할 수 있어 합당한 파라미터로써 사용할 수 있었다.

In conventional MOSFETs, the silicon thickness is always larger than inversion layer, so that the drain induced barrier lowering (DIBL) is expressed as a function of oxide thickness and channel length regardless of silicon thickness. However, since the silicon thickness is fully depleted in the sub-10 nm low doped double gate (DG) MOSFET, the conventional SPICE model for DIBL is no longer available. Therefore, we propose a novel DIBL SPICE model for DGMOSFETs. In order to analyze this, a thermionic emission and the tunneling current was obtained by the potential and WKB approximation. As a result, it was found that the DIBL was proportional to the sum of the top and bottom oxide thicknesses and the square of the silicon thickness, and inversely proportional to the third power of the channel length. Particularly, static feedback coefficient of SPICE parameter can be used between 1 and 2 as a reasonable parameter.

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참고문헌

  1. International Technology Roadmap for Semiconductors, 2015. [Internet] Available: http://www.itrs2.net/itrs-reports.html.
  2. ANANDTECH. Samsung and TSMC Roadmaps: 8 and 6 nm Added, Looking at 22ULP and 12FFC [Internet] http://www.anandtech.com/show/11337/samsung-and-tsmc-roadmaps-12-nm-8-nm-and-6-nm-added/2.
  3. J. Qu, H. Zhang, X. Xu, and S. Qin, "Study of Drain Induced Barrier Lowering(DIBL) Effect for Srained Si nMOSFET," Procedia Engineering, vol. 16, pp. 298-305, Nov. 2011. https://doi.org/10.1016/j.proeng.2011.08.1087
  4. T. Yamada, Y. Nakajima, T. Hanajiri, and T. Sugano, "Suppression of Drain-Induced Barrier Lowering in Silicon-on-lnsulator MOSFETs Through Source/Drain Engineering for Low Operating Power System on Chip Applications," IEEE Transactions On Electron Devices, vol. 60, no. 1, pp. 260-267, January 2013. https://doi.org/10.1109/TED.2012.2225063
  5. S. Dimitrijev, Principles of Semiconductor Devices, 2nd ed., New York, Oxford University Press, 2012.
  6. G. Massobrio, and P. Antognetti, Semiconductor Device Modeling with SPICE, 2nd ed., New York, McGraw-Hill, 1993.
  7. Z. Ding, G. Hu, J. Gu, R. Liu, L. Wang and T. Tang,"An analytical model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETs," Microelectronics Journal, vol. 42, no. 3, pp.515-519, March 2011. https://doi.org/10.1016/j.mejo.2010.11.002
  8. H. K. Jung, "Influence of Tunneling Current on Treshold Voltage Shift by Channel Length for Asymmetric Double Gate MOSFET," Journal of Korea Institute of Information and Communication Engineering, vol. 20, no. 7, pp. 1311- 1316, July 2016. https://doi.org/10.6109/jkiice.2016.20.7.1311
  9. H. K. Jung, and S. Dimitrijev, "Optimum top and bottom thickness and flat-band voltage for improving subthreshold characteristics of 5 nm DGMOSFET," Superlattices and Microstructures, vol. 101, no. 1, pp. 285-292, January 2017. https://doi.org/10.1016/j.spmi.2016.11.040
  10. H. K. Jung, "Top and Bottom Gate Oxide Thickness Dependent DIBL of Asymmetric Double Gate MOSFET," Information, vol. 19, no. 6(A), pp. 2021-2026, June 2016.