The Transactions of The Korean Institute of Electrical Engineers (전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
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Characteristics of Nanowire CMOS Inverter with Gate Overlap

Gate Overlap에 따른 나노선 CMOS Inverter 특성 연구

  • Yoo, Jeuk (Dept. of Electrical Engineering, Korea University) ;
  • Kim, Yoonjoong (Dept. of Electrical Engineering, Korea University) ;
  • Lim, Doohyeok (Dept. of Electrical Engineering, Korea University) ;
  • Kim, Sangsig (Dept. of Electrical Engineering, Korea University)
  • Received : 2017.05.02
  • Accepted : 2017.09.22
  • Published : 2017.10.01
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Abstract

In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage ($V_{dd}$) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high $I_{on}/I_{off}$ ratios are major factors that enable the excellent operation of the logic gate.

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References

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