ETRI Journal

  • 제39권3호
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  • Pages.373-382
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  • 2017
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  • 1225-6463(pISSN)
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  • 2233-7326(eISSN)
한국전자통신연구원 (Electronics and Telecommunications Research Institute)
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FVF-Based Low-Dropout Voltage Regulator with Fast Charging/Discharging Paths for Fast Line and Load Regulation

  • 투고 : 2016.10.27
  • 심사 : 2017.03.08
  • 발행 : 2017.06.01
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초록

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of $433.80{\mu}V/mA$ and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of $1{\mu}s$. The total current consumption is $17.88{\mu}V/mA$ (for a 0.9 V supply voltage).

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참고문헌

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