Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Scalable RSA public-key cryptography processor based on CIOS Montgomery modular multiplication Algorithm

CIOS 몽고메리 모듈러 곱셈 알고리즘 기반 Scalable RSA 공개키 암호 프로세서

  • Cho, Wook-Lae (School of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Shin, Kyung-Wook (School of Electronic Engineering, Kumoh National Institute of Technology)
  • Received : 2017.09.07
  • Accepted : 2018.01.05
  • Published : 2018.01.31
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Abstract

This paper describes a design of scalable RSA public-key cryptography processor supporting four key lengths of 512/1,024/2,048/3,072 bits. The modular multiplier that is a core arithmetic block for RSA crypto-system was designed with 32-bit datapath, which is based on the CIOS (Coarsely Integrated Operand Scanning) Montgomery modular multiplication algorithm. The modular exponentiation was implemented by using L-R binary exponentiation algorithm. The scalable RSA crypto-processor was verified by FPGA implementation using Virtex-5 device, and it takes 456,051/3,496347/26,011,947/88,112,770 clock cycles for RSA computation for the key lengths of 512/1,024/2,048/3,072 bits. The RSA crypto-processor synthesized with a $0.18{\mu}m$ CMOS cell library occupies 10,672 gate equivalent (GE) and a memory bank of $6{\times}3,072$ bits. The estimated maximum clock frequency is 147 MHz, and the RSA decryption takes 3.1/23.8/177/599.4 msec for key lengths of 512/1,024/2,048/3,072 bits.

512/1,024/2,048/3,072 비트의 4가지 키 길이를 지원하는 scalable RSA 공개키 암호 프로세서를 설계하였다. RSA 암호의 핵심 연산블록인 모듈러 곱셈기를 CIOS (Coarsely Integrated Operand Scanning) 몽고메리 모듈러 곱셈 알고리듬을 이용하여 32 비트 데이터 패스로 설계하였으며, 모듈러 지수승 연산은 Left-to-Right (L-R) 이진 멱승 알고리듬을 적용하여 구현하였다. 설계된 RSA 암호 프로세서를 Virtex-5 FPGA로 구현하여 하드웨어 동작을 검증하였으며, 512/1,024/2,048/3,072 비트의 키 길이에 대해 각각 456,051/3,496,347/26,011,947/88,112,770 클록 사이클이 소요된다. $0.18{\mu}m$ CMOS 표준셀 라이브러리를 사용하여 100 MHz 동작 주파수로 합성한 결과, 10,672 GE와 $6{\times}3,072$ 비트의 메모리로 구현되었다. 설계된 RSA 공개키 암호 프로세서는 최대 동작 주파수는 147 MHz로 예측되었으며, 키 길이에 따라 RSA 복호 연산에 3.1/23.8/177/599.4 ms 가 소요되는 것으로 평가되었다.

Keywords

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