Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Implementation and Performance Evaluation of PCI express on Xilinx FPGA

Xilinx FPGA용 PCI express 구현 및 성능 분석

  • Lee, Jin (Department of Information and Communication, Pyeongtaek University)
  • Received : 2018.11.12
  • Accepted : 2018.11.20
  • Published : 2018.12.31
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Abstract

Recently, speeding up real time calculation using the specialized hardware accelerator is often used in the various engineering and science area, and the accelerators are required to include PCI express interconnection between FPGA and a host computer. The implementation of the high speed PCIe for the multi-giga bytes per second transmission is one of the most difficult issue in the development of the accelerators. There are several commercialized IP solutions and research results in the literature, but these solutions are required extra cost and design period to analyze the detailed implementation method. For the hardware accelerator on Xilinx FPGA, utilizing Xilinx's XDMA PCIe IP, which is provided without extra charge, can be the best solution in terms of the development period and cost. Consequently, this paper presents the evaluation system on Zynq-7000 FPGA and Windows 10 host computer, and analyze the performance of the PCIe IP with various configuration parameters.

하드웨어 가속기를 사용하여 다양한 실시간 계산을 하는 여러 공학/과학 분야에서 많은 경우에 FPGA와 호스트 컴퓨터를 PCI express(PCIe)로 연결하는 시스템 구성이 요구된다. 하지만, 초당 수 기가바이트의 데이터를 주고 받는 고속 인터페이스인 PCIe의 구현은 하드웨어 가속기 개발의 가장 큰 어려움 중에 하나이다. 상용 제품과 논문을 통해서 여러 PCIe IP 솔루션을 찾을 수 있지만, 고가의 비용을 지불해서 구매하거나, 별도의 시간과 노력을 투자해서 PCIe를 구현해야 한다. 따라서, Xilinx사의 FPGA를 기반의 하드웨어 가속기를 구현할 때는 Xilinx사에서 무료로 제공 하는 XDMA PCIe IP를 사용하는 것이 개발 기간 및 비용 단축을 위한 최선의 선택이 될 수 있다. 이러한 이유로 본 논문에서는 Xilinx사의 PCIe IP의 성능 평가를 위해 Zynq-7000 FPGA개발보드와 Windows 10 호스트 컴퓨터로 평가 시스템을 구성하고, PCIe IP의 구성 파라미터에 의한 전송 속도 성능 변화에 대해 평가 분석한다.

Keywords

HOJBC0_2018_v22n12_1667_f0001.png 이미지

Fig. 1 The layers of PCI Express architecture.

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Fig. 2 Transaction layer packet (TLP).

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Fig. 3 Topology of PCI Express system[12].

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Fig. 4 Basic options for Xilinx XDMA IP.

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Fig. 5 Xilinx ZC706 EVM board [11].

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Fig. 6 Block diagram of XDMA evaluation system

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Fig. 7 PCIe throughput vs. internal memory size.

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Fig. 8 Write throughputs with different AXI options

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Fig. 10 Write throughputs with different memory widths

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Fig. 9 Read throughputs with different AXI options

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Fig. 11 Read throughputs with different memory widths

Table. 1 FPGA PCIe framework comparison.

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Table. 2 PCIe solution portfolio in Xilinx FPGA.

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Table. 3 Performance with different memory widths

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