Fig. 1. Block diagram of a tile (Jeffers et al., 2016, used with permission).
Fig. 2. Block diagram showing overview of Xeon Phi x200 Architecture (Jeffers et al., 2016, used with permission).
Fig. 3. A time-domain modeling algorithm.
Fig. 4. Parallelization using MPI processes (left) and OpenMP threads (right). Each number of star shows the rank of a process who performs a shot simulation. Each number on a grid shows the ID of a thread who calculates the wavefield on each grid block.
Fig. 5. Speed-ups using OpenMP with respect to the calculation times using one CPU core.
Table 1. Comparison of calculation times depending on the number of OpenMP threads, precision and order of FDM (s).
Table 2. Calculation times without high bandwidth memory on the Xeon Phi processor.
Table 3. Calculation times using both MPI and OpenMP.
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