The Journal of the Korea institute of electronic communication sciences (한국전자통신학회논문지)

Korea Institute of Electronic Communication Science (한국전자통신학회)
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Implementation of an FPGA-based Frame Grabber System for PCB Pattern Detection

PCB 패턴 검출을 위한 FPGA 기반 프레임 그래버 시스템 구현

  • 문철홍 (광주대학교 전기전자공학부)
  • Received : 2018.01.22
  • Accepted : 2018.04.15
  • Published : 2018.04.30
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Abstract

This study implemented an FPGA-based system to extract PCB defect patterns. The FPGA-based system can perform pattern matching at high speed for vision automation. An image processing library that is used to extract defect patterns was also implemented in IPs to optimize the system. The IPs implemented are Camera Link IP, Histogram IP, VGA IP, Horizontal Projection IP and Vertical Projection IP. In terms of hardware, the FPGA chip from the Vertex-5 of Xilinx was used to receive and handle images that are sent from a digital camera. This system uses MicroBlaze CPU. The image results are sent to PC and displayed on a 7inch TFT-LCD and monitor.

본 논문에서는 FPGA를 기반으로 Camera Link (Medium)를 제공하는 PCB 패턴 검출 시스템을 구현하였다. 시스템 구현을 위해 비전 라이브러리를 IP로 구현하여 고속으로 패턴 매칭을 할 수 있도록 하였다. 구현된 IP는 영상입력용 카메라링크 IP, 히스토그램 IP, VGA 제어 IP, 수직투영 IP 및 수평투영 IP가 있다. 디지털 카메라에서 고속으로 전송되는 영상을 처리하기 위해 Xilinx사의 Virtex-5 계열의 FPGA 칩을 사용하였다. 그래버 시스템 구현을 위해 RISC 구조의 CPU인 MicroBlaze를 사용하였으며, PC와의 연동을 위해 PCI Express를 사용하였으며, 영상의 처리결과는 컴퓨터의 모니터와 7인치 LCD에 표현하였다.

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