Journal of Electrical Engineering and Technology

  • 제13권3호
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  • Pages.1251-1264
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  • 2018
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  • 1975-0102(pISSN)
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  • 2093-7423(eISSN)
대한전기학회 (The Korean Institute of Electrical Engineers)
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Implementation of Zero-Ripple Line Current Induction Cooker using Class-D Current-Source Resonant Inverter with Parallel-Load Network Parameters under Large-Signal Excitation

  • Ekkaravarodome, Chainarin (Advanced Power Electronics and Experiment Laboratory (APEx Lab), Dept. of Instrumentation and Electronics Engineering, King Mongkut's University of Technology North Bangkok) ;
  • Thounthong, Phatiphat (Renewable Energy Research Centre (RERC), Dept. of Teacher Training in Electrical Engineering, King Mongkut's University of Technology North Bangkok) ;
  • Jirasereeamornkul, Kamon (Dept. of Electronic and Telecommunication Engineering, King Mongkut's University of Technology Thonburi)
  • 투고 : 2017.03.22
  • 심사 : 2018.01.26
  • 발행 : 2018.05.01
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초록

The systematic and effective design method of a Class-D current-source resonant inverter for use in an induction cooker with zero-ripple line current is presented. The design procedure is based on the principle of the Class-D current-source resonant inverter with a simplified load network model that is a parallel equivalent circuit. An induction load characterization is obtained from a large-signal excitation test-bench based on parallel load network, which is the key to an accurate design for the induction cooker system. Accordingly, the proposed scheme provides a systematic, precise, and feasible solution than the existing design method based on series-parallel load network under low-signal excitation. Moreover, a zero-ripple condition of utility-line input current is naturally preserved without any extra circuit or control. Meanwhile, a differential-mode input electromagnetic interference (EMI) filter can be eliminated, high power quality in utility-line can be obtained, and a standard-recovery diode of bridge-rectifier can be employed. The step-by-step design procedure explained with design example. The devices stress and power loss analysis of induction cooker with a parallel load network under large-signal excitation are described. A 2,500-W laboratory prototype was developed for $220-V_{rms}/50-Hz$ utility-line to verify the theoretical analysis. An efficiency of the prototype is 96% at full load.

키워드

참고문헌

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