The Journal of Korea Institute of Information, Electronics, and Communication Technology (한국정보전자통신기술학회논문지)

Korea Information Electronic Communication Technology (한국정보전자통신기술학회)
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Spur Reduced PLL with △Σ Modulator and Spur Reduction Circuit

델타-시그마 변조기와 스퍼 감소 회로를 사용하여 스퍼 크기를 줄인 위상고정루프

  • Choi, Young-Shig (Department of Electronic Engineering, Pukyong National University) ;
  • Han, Geun-Hyeong (Department of Electronic Engineering, Pukyong National University)
  • Received : 2018.09.18
  • Accepted : 2018.10.11
  • Published : 2018.10.30
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Abstract

A novel PLL with a delta-sigma modulator and a spur reduction circuit is proposed. delta-sigma modulator makes the LF remove noise easily by moving the spur noise to a higher frequency band. Therefore, the magnitude of spur can be reduced the reasonable bandwidth. The spur reduction circuit reduces the spur size by reducing the LF voltage change generated during the period of reference signal. The spur reduction circuit is designed as simple as possible not to increase the size of PLL. The proposed PLL with the previous two techniques is designed with a supply voltage of 1.8V in a 0.18um CMOS process. Simulation results show an almost 20dB reduction in the magnitude of spur. The spur reduced PLL can be used in narrow bandwidth communication system.

스퍼의 크기를 줄이기 위해 델타-시그마 변조기와 스퍼감소회로가 도입된 위상고정루프(PLL)를 제안하였다. 델타-시그마 변조기는 스퍼 잡음을 높은 주파수 대역으로 이동시켜 루프필터가 잡음 제거를 쉽게 할 수 있도록 해준다. 이는 위상고정루프의 대역폭을 적절히 조절하면 스퍼 크기를 크게 감소시킬 수 있다. 스퍼감소회로는 한주기당 발생하는 루프필터 전압변화를 작게 하여 스퍼 크기가 감소되도록 한다. 제안한 스퍼감소회로는 위상고정루프의 크기에 거의 영향이 없을 정도로 간단하게 설계하였다. 이 두 가지 방법을 사용한 제안된 위상고정루프는 $0.18{\mu}m$ CMOS 공정에서 1.8V의 공급전압으로 설계되었으며, 시뮬레이션을 통해 제안된 위상고정루프의 스퍼 크기가 거의 20dB 감소된 것을 확인하였다. 스퍼의 크기가 크게 감소된 위상고정루프는 대역폭이 좁은 통신시스템에 크게 활용될 수 있다.

Keywords

References

  1. Y. Lee, T. Seong, S. Yoo, and J. Choi, "A -242-dB FOM and -71-dBc reference spur ring VCO based ultra low jitter switched loop filter PLL using a fast phase-error correction technique", VLSI Circuits Symposium on, pp. 186 - 187, 2017.
  2. A. Rao, M. Mansour, G. Singh, C. Lim, R. Ahmed, and D. R. Johnson, "A 4-6.4 GHz LC PLL with adaptive bandwidth control for a forward clock link", IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2099-2108, Sept. 2008. https://doi.org/10.1109/JSSC.2008.2001870
  3. W. B. Wilson, U. Moon, K. R. Lakshmikumar, and L. Dai, "A CMOS self-calibrating frequency synthesizer", IEEE Journal of Solid-State Circuits, vol. 35, pp. 1437-1444, Oct. 2000. https://doi.org/10.1109/4.871320
  4. Wu-Hsin Chen, Wing-Fai Loke, and Byunghoo Jung, "A 0.5-V, 440-${\mu}$ W Frequency Synthesizer for Implantable Medical Devices", IEEE Journal of Solid-State Circuits, vol. 47, no. 8, pp. 1896 - 1907, Aug. 2012. https://doi.org/10.1109/JSSC.2012.2196315
  5. M. M. Elsayed, M. Abdul-Latif, E. Sanchez-Sinecio," A spur - frequency - boosting PLL with a -74 dBc reference-spur suppression in 90 nm digital CMOS", IEEE Journal of Solid-State Circuits, vol. 48, no. 9, pp. 2104-2117, Sept. 2013. https://doi.org/10.1109/JSSC.2013.2266865
  6. M. Kobayashi, Y. Masui, T. Kihara and T. Yoshimura, "Spur Reduction by Self-Injection Loop in a Fractional-N PLL", 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2017.
  7. C.-R Ho and , M.S.W. Chen, "A Digital PLL with Feedforward Multi-Tone Spur Cancelation Loop Achieving <-73dBc Fractional Spur and <-110dBc Reference Spur in 65nm CMOS", IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 3216-3230, Feb. 2016. https://doi.org/10.1109/JSSC.2016.2596770
  8. M. Zackriya V, J. Reuben, H. M Kittur, "A low power dual modulus prescaler for fractional-N PLL synthsizer", Electronics and Communication Systems (ICECS), pp. 1-4, Feb., 2014.
  9. Y. Zhang, J. H. Mueller, B. Mohr, L. Liao, A. Atac, R. Wunderlich, S. Heinen, "A Multi-Frequency Multi-Standard Wideband Fractional-N PLL With Adaptive Phase-Noise Cancellation for Low-Power Short-Range Standards ", IEEE Transactions on Microwave Theory and Techniques, vol. 64, pp. 1133-1142, Apr., 2016. https://doi.org/10.1109/TMTT.2016.2536022
  10. E. Temporiti, G. Albasini, R. Castello, and M. Colombo, "A 700-KHz bandwidth ${\Delta}\Sigma$ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications", IEEE J, Solid-State Circuit, vol. 39, pp. 1446-1454, Sept., 2004. https://doi.org/10.1109/JSSC.2004.831598