The Transactions of The Korean Institute of Electrical Engineers (전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
권호 표지
DOI QR코드

DOI QR Code

The Design of Robust DSC-PLL under Distorted Grid Voltage Contained Unbalance on Frequency Variation

주파수 변동시 불평형 전압에 강인한 DSC-PLL 설계 연구

  • Lee, Jae Do (Korea Institute of Nuclear Safety) ;
  • Cha, Han Ju (Dept. of Electrical Engineering Chungnam National University)
  • Received : 2018.09.15
  • Accepted : 2018.10.11
  • Published : 2018.11.01
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, the design of robust DSC-PLL(Delayed Signal Cancellation Phase Locked Loop) is proposed for coping with frequency variation. This method shows significant performance for detection of fundamental positive sequence component voltage when the grid voltage is polluted by grid unbalance and frequency variation. The feedback frequency estimation of DSC-PLL is tracking the drift in the phase by unbalance and frequency variation. The robust DSC PLL is to present the analysis on method and performance under frequency variations. These compensation algorithms can correct for discrepancies of changing the frequency within maximum 193[ms] and improve traditional DSC-PLL. Linear interpolation method is adopted to reduce the discretized errors in the digital implementation of the PLL. For verification of robust characteristic, PLL methods are implemented on FPGA with a discrete fixed point based. The proposed method is validated by both Matlab/Simulink and experimental results based on FPGA(XC7Z030).

Keywords

References

  1. D. W. P. Thomas and M. S. Woolfson, "Evaluation of frequency tracking methods", IEEE Trans. Power Delivery, vol. 16, pp. 367-371, July 2001.
  2. Digital PLL control for grid connected solar power system, KIEE Trans, pp. 562-568, Sept 2004.
  3. S. K. Chung, "A phase tracking system for three phase utility interface inverters", IEEE Trans, Power Electron., vol. 15, no. 3, pp. 431-438, May 2000. https://doi.org/10.1109/63.844502
  4. "Grid harmonics and Voltage Unbalance Effect Elimination for Three-Phase PLL Grid Synchronization Algorithm", Energy Conversion Congress and Exposition (ECCE), 2013 IEEE, Sept. 2013, pp. 3299-3304.
  5. P. Rodiruez, J. Pou, J. Bergas, J. I. Candela, R. P. Burgo, and D. Boroyevinh, "Decoupled Doubled Synchronous Reference Frame PLL for Power Converters Control", IEEE Trans. Power Electron., vol. 22, pp. 584-592, May 2007.
  6. P. Rodriguez, A. Luna, I. Candela, R. Teodorescu, and F. Blaabjerg, "Grid Synchronization of Power Converters using Multiple Second Order Generalized Integrators", Industrial Electronics, 2008. IECON 2008. 34th Annual Conference of IEEE ,Nov.2008, pp.755-760.
  7. M. K. Ghartemani, M. R. Iravani, "A method for synchronization of power electronic converters in polluted and variable-frequency environments", IEEE Trans. Power Syst., vol. 19, No. 3, Aug. 2004.
  8. Ziwen Yao, "Fundamental Phasor Calculation With Short Delay", IEEE Trans. Power Del., vol. 23, pp. 1280-1287, July. 2008.
  9. J. Svensson, M. Bongiorno and A. Sannino, "Practical implementation of delayed signal cancellation method for phase-sequence separation", IEEE Trans. Power Del., vol. 22, no 1, pp. 18-26, Jan. 2007. https://doi.org/10.1109/TPWRD.2006.881469
  10. Y. F. Wang and Y. W. Li, "Grid Synchronization PLL Based on Cascaded Delayed Signal Cancellation", IEEE Trans. Power Electron., vol. 26, pp. 1987-1997, July 2011. https://doi.org/10.1109/TPEL.2010.2099669
  11. Y.F. Wang and Y. W. Li, "Analysis and Digital Implementation of Cascaded Delayed-Signal-Cancellation PLL", IEEE Trans. Power Electron, vol. 26, pp. 1067-1080, April 2011. https://doi.org/10.1109/TPEL.2010.2091150
  12. Qicheng Huang and Kaushik Rajashekara "An Improved Delayed Signal Cancellation PLL for Fast Grid Synchronization under Distorted and Unbalanced Grid Condition", IEEE Trans. on Industry Applications, vol. 53, pp. 4985-4997, October 2017. https://doi.org/10.1109/TIA.2017.2700282
  13. Jongmin Jo, Byung-Moon Han, Hanju Cha "FPGA based DSC-PLL for grid harmonics and voltage unbalance effect elimination", 2015 IEEE Applied Power Electronics Conference and Exposition (APEC) pp. 2212-2216, 2015.