한국전자통신학회논문지 (The Journal of the Korea institute of electronic communication sciences)

한국전자통신학회 (Korea Institute of Electronic Communication Science)
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4비트 ADC 반복구조를 이용한 저전력 전류모드 12비트 ADC

A Low Power Current-Mode 12-bit ADC using 4-bit ADC in cascade structure

  • 박소연 (서울과학기술대학교 전자IT미디어공학과) ;
  • 김형민 (서울과학기술대학교 대학원) ;
  • 이대니얼주헌 (서울과학기술대학교 대학원) ;
  • 김성권 (서울과학기술대학교 전자IT미디어공학과)
  • 투고 : 2019.10.10
  • 심사 : 2019.12.15
  • 발행 : 2019.12.31
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초록

본 논문에서는 디지털 회로와 저소비전력 및 고속연산의 장점을 가진 아날로그 회로를 혼용하기 위하여, 저전력 전류모드 12비트 ADC(: Analog to Digital Converter)를 제안하였다. 제안하는 12비트 ADC는 4비트 ADC의 cascade 구조를 사용하여 소비전력을 줄일 수 있었으며, 변환 current mirror 회로를 사용해 칩면적을 줄일 수 있었다. 제안된 ADC는 매그나칩/SK하이닉스 350nm 공정으로 구현하였고, Cadence MMSIM을 사용하여 post-layout simulation를 진행하였다. 전원전압 3.3V에서 동작하고, 면적은 318㎛ x 514㎛를 차지하였다. 또한 제안하는 ADC는 평균 소비전력 3.4mW의 저소비전력으로 동작하는 가능성을 나타내었다.

In this paper, a low power current mode 12-bit ADC(: Analog to Digital Converter) is proposed to mix digital circuits and analog circuits with the advantages of low power consumption and high speed operation. The proposed 12 bit ADC is implemented by using 4-bit ADC in a cascade structure, so its power consumption can be reduced, and the chip area can be reduced by using a conversion current mirror circuit. The proposed 12-bit ADC is SK Hynix 350nm process, and post-layout simulation is performed using Cadence MMSIM. It operates at a supply voltage of 3.3V and the area of the proposed circuit is 318㎛ x 514㎛. In addition, the ADC shows the possibility of operating with low power consumption of 3.4mW average power consumption in this paper.

키워드

참고문헌

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