Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Area-Efficient Semi-Parallel Encoding Structure for Long Polar Codes

긴 극 부호를 위한 저 면적 부분 병렬 극 부호 부호기 설계

  • Shin, Yerin (Dept. of Electronics Engineering, Chungnam national University) ;
  • Choi, Soyeon (Dept. of Electronics Engineering, Chungnam national University) ;
  • Yoo, Hoyoung (Dept. of Electronics Engineering, Chungnam national University)
  • Received : 2019.12.19
  • Accepted : 2019.12.26
  • Published : 2019.12.31
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Abstract

The channel-achieving property made the polar code show to advantage as an error-correcting code. However, sufficient error-correction performance shows the asymptotic property that is achieved when the length of the code is long. Therefore, efficient architecture is needed to realize the implementation of very-large-scale integration for the case of long input data. Although the most basic fully parallel encoder is intuitive and easy to implement, it is not suitable for long polar codes because of the high hardware complexity. Complementing this, a partially parallel encoder was proposed which has an excellent result in terms of hardware area. Nevertheless, this method has not been completely generalized and has the disadvantage that different architectures appear depending on the hardware designer. In this paper, we propose a hardware design scheme that applies the proposed systematic approach which is optimized for bit-dimension permutations. By applying this solution, it is possible to design a generalized partially parallel encoder for long polar codes with the same intuitive architecture as a fully parallel encoder.

Polar code의 채널용량 달성 특성은 polar code를 각광 받는 오류 정정 부호로 만들었다. 하지만 충분한 오류 정정 성능은 부호의 길이가 길어졌을 때 달성되는 점근적 속성을 보인다. 따라서 입력 데이터가 길어지는 경우에 대한 초대규모 집적회로 구현을 실현하기 위하여 효율적인 구조가 필요하게 되었다. 기존의 polar code 부호기 구조 중 가장 기본적인 완전 병렬 구조는 직관적이고 구현이 쉽지만 긴 polar code에 높은 하드웨어 복잡성을 보이므로 부적합하다. 그리고 이를 보완하여 제안된 부분 병렬 구조는 하드웨어 면적 측면에서 큰 성과를 얻었으나 그 방식이 일반화되어 있지 않아 설계자에 따라 구조에 변동이 발생할 수 있다. 본 논문에서는 이를 개선하고자 비트 차원의 치환을 위해 제안된 회로 설계법을 polar code에 적용하는 하드웨어 설계법을 제안한다. 제안하는 방법을 polar code의 부호기에 적용함으로써 완전 병렬 부호기만큼 직관적인 구조를 가짐과 동시에 일반화된 polar code 부분 병렬 부호기를 설계할 수 있다.

Keywords

References

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