Zero-Current-Switching in Full-Bridge DC-DC Converters Based on Activity Auxiliary Circuit

Abstract

To address the problem of circulating current loss in the traditional zero-current switching (ZCS) full-bridge (FB) DC/DC converter, a ZCS FB DC/DC converter topology and modulation strategy is proposed in this paper. The strategy can achieve ZCS turn on and zero-voltage and zero-current switching (ZVZCS) turn off for the primary switches and realize ZVZCS turn on and zero-voltage switching (ZVS) turn off for the auxiliary switches. Moreover, its resonant circuit power is small. Compared with the traditional phase shift full-bridge converter, the new converter decreases circulating current loss and does not increase the current stress of the primary switches and the voltage stress of the rectifier diodes. The diodes turn off naturally when the current decreases to zero. Thus, neither reverse recovery current nor loss on diodes occurs. In this paper, we analyzed the operating principle, steady-state characteristics and soft-switching conditions and range of the converter in detail. A 740 V/1 kW, 100 kHz experimental prototype was established, verifying the effectiveness of the converter through experimental results.

I. INTRODUCTION

With the advantages of simple topology, easy control, and high efficiency, the full-bridge converter is widely used in high-power applications, such as power supply, renewable energy, and electric vehicle traction systems [1], [2]. Soft-switching technology has the following advantages: improving operating environment and reliability of power switches, reducing power losses and sizes of converters, enhancing efficiency, suppressing the exorbitant dv/dt and di/dt, and cutting down electromagnetic interference (EMI) and system noise effectively [3]-[5].

Traditional phase shift zero-voltage full-bridge DC–DC converters [6], [7] can solve the problem of hard-switching of the primary switch, but the lagging switches are suffering from realizing soft-switching difficultly under the light load condition, thereby limiting the load range of the converter. To solve this problem, various zero-voltage and zero-current switching (ZVZCS) full-bridge converters [8]-[11] based on auxiliary circles were proposed. The leading switch realizes ZVS and the lagging switch realizes ZCS. It widens the soft-switching range and reduces the switching loss of the lagging switch, but the leading switch does not realize the ZCS turn off. The great switching loss in the primary switch still exists.

In order to solve the problem of great switching loss in the primary switch, zero-current switching full-bridge converters have been proposed in [12]-[14]. To achieve ZCS turn off of the primary switch, the auxiliary switch and additional transformer is added to the primary switch in [12]. Unfortunately, the additional transformer increases the magnetic loss and the volume of the converter. In [13], two auxiliary switches are connected in parallel in the secondary to achieve ZCS turn off of the primary switch of the converter. However, ZCS turn off is only achieved under a discontinuous conduction mode, and the auxiliary switches are hard turn off, thereby increasing the total losses of converters. The reference [14] proposed to add an active auxiliary circle in the primary and a passive snubber circuit on the secondary side of the converter, respectively, to achieve the ZCS turn-off of the leading switch and the ZCS turn-off of the lagging switch. Unfortunately, these auxiliary circuits are complex and increase the current and voltage stress of the power switches; moreover, they result in additional circulating current loss.

To solve the aforementioned issues, a ZCS full-bridge DC/DC converter and modulation strategy is proposed in this paper. The converter realizes ZCS turn-on and ZVZCS turn-off of primary switches and achieves ZVZCS turn-on and ZVS turn-off of auxiliary switches. The converter decreases circulating current loss and does not increase the current stress of the primary switches and the voltage stress of the rectifier diodes. The diodes turn off naturally when the current decreases to zero. Thus, no reverse recovery current and loss occurs on diodes. The converter improves the conversion efficiency of high-frequency high-power applications.

This paper analyzed the operating principle, steady-state characteristics, soft-switching conditions, and range, and conducts parameter design and loss analysis of the converter in detail. A 740 V/1 kW, 100 kHz experimental prototype was established, thereby verifying the effectiveness of the converter by experimental results.

II. CIRCUIT TOPOLOGY AND OPERATION PRINCIPLE

Fig. 1 shows the proposed ZCS full-bridge converter topology, where V_in is the input DC voltage source. Switches S₁–S₄, and antiparallel diodes D₁–D₄ consist of the full bridge inverter structure; L_r is the leakage inductance of T or the summation of the leakage inductance and an external inductance. The auxiliary switches S₅ and S₆ in parallel with the resonant capacitor C_r are connected in series with the secondary circuit. D₅ and D₆ are antiparallel diodes of the switches S₅ and S₆. The diodes D_R1–D_R4 are the secondary output rectifier diodes. T is the high frequency transformer. L_o is the output filter inductance. C_o is the output filter capacitor, and R is the load. i_p is the primary current, i_s is the secondary current, and v_Cr is the auxiliary resonant capacitor voltage.

Fig. 1. The proposed ZCS full-bridge converter.

Fig. 2 and Fig. 3 respectively show the working waveforms and operation modes of the proposed converter. In Fig.2, v_g1/v_g4 and v_g2/v_g3 are the driving waveforms of S₁/S₄ and S₂/S₃, respectively. v_g5 and v_g6 are the driving waveforms of S₅ and S₆, respectively. S₁/S₂ and S₄/S₃ turn off after S₅/S₆ turn off with off delay time t_δ. t_d is the dead time between S₁ and S₂ as well as S₃ and S₄. T_s is a switching period. t_on is the conduction time of the primary switches. D_in is the converter input duty cycle expressed as D=t_on/T_h, D is the converter output duty cycle expressed as D=(t_on-t_δ)/T_h, where T_h = T_s/2.

Fig. 2. Working waveforms of the proposed converter.

To facilitate the analysis, several assumptions are used as follows:

(1) All the switches, diodes, capacitors and inductors are ideal devices.

(2) N₁ and N₂ are the turns of the transformer’s primary and secondary, respectively. The transformer turn ratio N_T is N₁/N₂. The roll line resistance of the transformer is neglected.

(3) The output inductance L_o is sufficiently large to keep the filter inductor current i_Lo at a constant value I_o during the switching period.

Mode 0 [~t₀] [see Fig. 3(a)]: Prior to t₀, the primary switches S₁–S₄ are off, the auxiliary switch S₆ is off and S₅ is on, the initial voltage of the auxiliary resonant capacitor C_r is v_Cr=0. The rectifier diodes D_R1–D_R4 are on. The load current flows through rectifier diodes for freewheeling.

Mode 1 [t₀–t₁] [see Fig. 3(b)]: At t₀, S₁ and S₄ turn on. i_p and i_s increase linearly. L_r limits the increase rate of i_p; thus, S₁ and S₄ realize ZCS turn on. When i_s increases to I_o, D_R2, and D_R3 turn off, and mode 1 ends.

i_p is described as

\(i_{p}=\frac{V_{i n}}{L_{r}}\left(t-t_{0}\right)\)       (1)

The duration time of this mode is

\(t_{01}=\frac{I_{o} L_{r}}{N_{T} V_{i n}}\)       (2)

Mode 2 [t₁–t₂] [see Fig. 3(c)]: At t₁, D_R2 and D_R3 are turned off. The power is delivered from the input DC voltage source to the load.

Mode 3 [t₂–t₃] [see Fig. 3(d)]: At t₂, S₆ turns on under ZVZCS, and S₅ as well as D₆ turn off simultaneously. C_r is charged by load current, vCr increases linearly from zero.

C_r paralleled with S₅ and D₆. Thus, S₅ and D₆ turn off under ZVS. When v_Cr increases to the secondary voltage, the mode 3 ends.

v_Cr is expressed as

\(v_{c r}=\frac{I_{o}}{C_{r}}\left(t-t_{2}\right)\)       (3)

The time duration of this mode is

\(t_{23}=\frac{V_{i n} C_{r}}{I_{o} N_{T}}\)       (4)

Mode 4 [t₃–t₄] [see Fig. 3(e)]: At t₃, D_R2 and D_R3 turn on, v_d=0. The load current flows through the rectifier diodes for freewheeling. C_r resonates with L_r. Hence, i_p decreases, and v_Cr increases resonantly. When i_p decreases to zero, v_Cr increases to the maximum voltage V_Crmax, and Mode 4 ends.

The current through the rectifier diodes and i_Cr and v_Cr are expressed as

\(i_{D R 1}=\frac{I_{o}}{2}\left[1+\cos \frac{N_{T}}{\sqrt{L_{r} C_{r}}}\left(t-t_{3}\right)\right]\)       (5)

\(i_{D R 2}=\frac{I_{o}}{2}\left[1-\cos \frac{N_{T}}{\sqrt{L_{r} C_{r}}}\left(t-t_{3}\right)\right]\)       (6)

\(i_{C r}(t)=I_{o} \cos \frac{N_{T}}{\sqrt{L_{r} C_{r}}}\left(t-t_{3}\right)\)       (7)

\(v_{C r}=\frac{V_{i n}}{N_{T}}+\frac{I_{o}}{N_{T}} \sqrt{\frac{L_{k}}{C_{r}}} \sin \frac{N_{T}}{\sqrt{L_{r} C_{r}}}\left(t-t_{3}\right)\)       (8)

The maximum voltage V_Crmax is

\(V_{C r \max }=\frac{V_{i n}}{N_{T}}+\frac{I_{o}}{N_{T}} \sqrt{\frac{L_{r}}{C_{r}}}\)       (9)

The duration time of this mode is 1/4 resonant period, as follows:

\(t_{34}=\frac{\pi \sqrt{L_{r} C_{r}}}{2 N_{T}}\)       (10)

Mode 5 [t₄–t₅] [see Fig. 3(f)]: At t₄, D₁ and D₄ turn on, C_r continues to resonate with L_r, the voltage across S₁ and S₄ is clamped at zero. Consequently, ZVZCS turn off can be achieved in S₁ and S₄. i_p rises from zero in reverse, and v_cr decreases from the maximum voltage. The load current flows through the rectifier diodes for freewheeling.

i_p and v_Cr are expressed as

\(i_{p}(t)=\frac{I_{o}}{N_{T}} \sin \frac{N_{T}}{\sqrt{L_{r} C_{r}}}\left(t-t_{4}\right)\)       (11)

\(v_{C r}(t)=v_{C r \max }+\frac{I_{o}}{N_{T}} \sqrt{\frac{L_{r}}{C_{r}}}\left[\cos \frac{N_{T}}{\sqrt{L_{r} C_{r}}}\left(t-t_{4}\right)-1\right]\)       (12)

After 1/2 resonant period, i_p decreases to zero and v_cr decreases to V_Crmin, mode 5 ends.

The minimum voltage V_Crmin is

\(V_{C r \min }=\frac{V_{i n}}{N_{T}}-\frac{I_{o}}{N_{T}} \sqrt{\frac{L_{r}}{C_{r}}}\)       (15)

The duration time of this mode is 1/2 resonant period, namely,

\(t_{45}=\frac{\pi \sqrt{L_{r} C_{r}}}{N_{T}}\)       (14)

Mode 6 [t₅–t₆] [see Fig. 3(g)]: At t₅, i_p decreases to zero, D_R1 and D_R4 turn off. C_r is discharged by the output current. v_Cr decreases linearly. When v_Cr decreases to zero, mode 6 ends.

v_Cr is expressed as follows:

\(v_{C r}=v_{C r \min }-\frac{I_{o}}{C_{r}}\left(t-t_{5}\right)\)       (15)

The duration time of this mode is

\(t_{56}=\left(\frac{V_{i n}}{I_{o} N_{T}}-\frac{1}{N_{T}} \sqrt{\frac{L_{r}}{C_{r}}}\right) C_{r}\)       (16)

Mode 7 [t₆–t₇] [see Fig. 3(h)]: At t₆, v_Cr decreases to zero, D_R1 and D_R4 turn on. The load current flows through rectifier diodes for freewheeling.

Mode 7 ends when S₂ and S₃ turn on, and the converter starts with the second half switching cycle. Owing to the symmetrical configuration of the proposed converter, the analysis of the second half switching cycle is omitted.

Fig. 3. Equivalent circuits of different operation modes.

III. STEADY STATE CHARACTERISTICS

A. Output Voltage Characteristics

The waveforms of the rectifier voltage and the filter inductor current are shown in Fig. 4. The average value of the output voltage V_o approximately equal to that of the voltage v_d rectified by the transformer secondary rectifier diodes. Based on the waveform of v_d depicted in Fig. 4, V_o is given by the following:

\(V_{o}=\frac{1}{T_{h}} \int_{0}^{T_{h}} V_{d}(t) d t=\frac{V_{i n} D}{N_{T}}+\frac{V_{i n}^{2} C_{r}}{2 N_{T}^{2} I_{o} T_{h}}\)       (17)

Fig. 4. Waveforms of rectified voltage and output filter current.

According to (17), when the value of the resonant capacitor is near zero, the output voltage characteristics of the converter are the same as those of the hard-switching full-bridge converter. Fig 5 shows the effects of the different auxiliary resonant capacitor C_r on the output voltage characteristics under an open-loop control scheme when the output load R=10Ω (Fig. 5(a) and Fig. 5(b) are , the 2D and 3D plots). Clearly, the output voltage increases with the increasing in the auxiliary resonant capacitor C_r, which is beneficial to improve the voltage gain.

Fig. 5. Open loop output voltage (R_o=10Ω). (a) Two-dimensional plot. (b) Three-dimensional plot.

Fig. 6 shows the effect of different off delay time t_δ on the output voltage characteristics under an open-loop control scheme when the output load R=10Ω. Fig. 6 intuitively shows that the output voltage decreases as t_δ increases when the input duty ratio D_in is constant.

Fig. 6. Open loop output voltage with different t_δ (R_o=10Ω).

B. Maximum Current and Voltage Stresses of Components

The voltage and current stress on the main components of the proposed converter and the traditional phase shift full-bridge converter are shown in Table I.

TABLE I VOLTAGE AND CURRENT STRESS ON MAIN COMPONENTS OF THE REFERENCE CONVERTERS

From Table I, it can be seen that the current stress on the primary switches and the voltage stress on the rectifier diodes of the proposed converter are the same as that of the traditional phase shift full-bridge converter. Decreasing L_r or increasing C_r is beneficial to the reduction of voltage stress on the auxiliary switches under the same input voltage V_in, load current I_o, and ratio of the transformer N_T.

C. dv/dt of Auxiliary Switches and di/dt of Rectifier Diodes

According to (1) and (3), the voltage change rate dv/dt of auxiliary switches during turn-off transient. The current change rate di/dt of the rectifier diodes during primary switch turn-on transient can be obtained as follows:

\(\frac{d v}{d t}=\frac{I_{o}}{C_{r}}\)       (18)

\(\frac{d i}{d t}=\frac{V_{i n}}{L_{r}}\)       (19)

Based on (18) and (19), we know that the voltage change rate dv/dt of auxiliary switches during turn-off transient and the current change rate di/dt of the rectifier diodes during primary switch turn-on transient are constants. It illustrates that the voltage across the auxiliary switches during turn-off transient and the current through the rectifier diodes during primary switch turn-on transient are in linear variation, and these change rates can be designed arbitrarily in the parameter design.

IV. SOFT-SWITCHING IMPLEMENTATION CONDITION

A. ZCS Implementation Condition of Primary Switch

Based on the operation principle of the converter, it can be seen that t₂₄=t₂₃+t₃₄ and t₂₅=t₂₃+t₃₄+t₄₅ from Fig. 2 and Fig. 3. To achieve ZVZCS turn off for the primary switches, the off delay time t_δ should satisfy t₂₄≤t_δ≤t₂₅, according to(4), (10) and (14), t_δ can be expressed as

\(\frac{V_{i n} C_{r}}{N_{T} I_{o}}+\frac{\pi \sqrt{L_{r} C_{r}}}{2 N_{T}} \leq t_{\delta} \leq \frac{V_{i n} C_{r}}{N_{T} I_{o}}+\frac{3 \pi \sqrt{L_{r} C_{r}}}{2 N_{T}}\)       (20)

Based on (20), the off delay time t_δ is related to the input voltage V_in, the load current I_o, the auxiliary resonant capacitor C_r, and the resonant inductor L_r. Fig. 7 shows the influence of the parameter variation on the value range of the off delay time t_δ. Fig. 7(a) shows the influence of the variation range of C_r and L_r to the off delay time t_δ when V_in and I_o are constant. Fig. 7(b) shows the influence of the input voltage V_in and the load current I_o to the range of the off delay time t_δ when C_r and L_r are constant. As evident from Fig. 7, when the input voltage V_in and the load current I_o are constant, the value interval length of the off delay t_δ varies with the different value of C_r and L_r. The larger value of C_r and L_r, and the longer value interval length of t_δ. When C_r and L_r are constant, the value interval length of t_δ does not change with the input voltage V_in and the load current I_o.

Fig. 7. Range of off delay time t_δ. (a) Range of t_δ with different C_r and L_r. (b) Range of t_δ with different V_in and I_o.

Fig. 8 shows the range (t₂₄(I_omax)≤t_δ≤t₂₅(I_omax)) of the off delay time t_δ to realize the primary switches ZCS turn off under the maximum load current I_omax. The A area in the Fig. 8 is the soft switching area. Fig. 8 shows the larger the off delay time t_δ, the wider the soft switching range of load current.

Fig. 8. Soft switching range.

B. ZVS Implementation Condition of Auxiliary Switch

To achieve ZVZCS turn on for the auxiliary switches, the voltage v_Cr must drop to zero during the dead time t_d.

Thus, t_d should satisfy t_d≥t₅₆ according to(16), t_d can be expressed as

\(t_{d} \geq \frac{V_{i n} C_{r}}{I_{o} N_{T}}-\frac{\sqrt{L_{r} C_{r}}}{N_{T}}\)       (21)

C. Maximum Effective Duty Cycle

Owing to the existence of the resonant inductance L_r and the auxiliary resonant capacitor C_r, the effective duty cycle D_eff in the secondary is smaller than the duty cycle D_in in the primary. The difference is the duty cycle loss D_loss. During the period of [t₀,t₁ ] ([t₇,t₈]), negative voltage (positive voltage) occurs in the primary, but the primary is insufficient to provide for the load current. Therefore, the rectifier diodes D_R1–D_R4 are both conducting, and the secondary voltage v_d=0. During the period of [t₃,t₅] ([t₁₀,t₁₂]), negative voltage (positive voltage) in the primary, but series resonance occurs between the resonant inductance L_r and resonant capacitor C_r. The primary does not provide for the load. Therefore, the rectifier diodes D_R1–D_R4 are conducting, and the secondary voltage v_d=0. Thus, the voltage of [t₀,t₁], [t₃,t₅], [t₇,t₈], and [t₁₀,t₁₂] are lost in the secondary, so the ratio of this duration time to T_h is D_loss:

\(D_{l o s s}=\frac{t_{01}+t_{34}+t_{45}}{T_{h}}\)       (22)

Based on (2), (10) and (14),

\(D_{l o s s}=\frac{3 \pi \sqrt{L_{r} C_{r}}}{2 N_{T} T_{h}}+\frac{I_{o} L_{r}}{N_{T} V_{i n} T_{h}}\)       (23)

Considering the dead time and the duty cycle loss, the maximum effective duty cycle D_eff-max of the converter is:

\(D_{e f f-m a x}=1-D_{t d}-D_{l o s s}\)       (24)

Among it, D_td is expressed as

\(D_{t d}=\frac{t_{d}}{T_{h}}\)       (25)

Based on (23) and (25),

\(D_{e f f-\max }=1-\left(\frac{3 \pi \sqrt{L_{r} C_{r}}}{2 N_{T} T_{h}}+\frac{I_{o} L_{r}}{N_{T} V_{i n} T_{h}}+\frac{t_{d}}{T_{h}}\right)\)       (26)

V. POWER LOSS ANALYSIS

A. Power Components Loss

The losses of the proposed converter include the switching loss and conduction loss of switching elements and the other losses generated by transformer and inductance and capacitor. The primary switches that use IGBT are ZVZCS turn off; the auxiliary switches that use MOSFET are ZVZCS turn on. Therefore, the losses of the switching elements only include the conduction loss, and it consists of three parts.

1) Conduction Loss of the Primary Switches:

The conduction loss P_Q1-conl of switches Q₁/Q₂ includes the conduction loss P_S1-conl of switches S₁/S₂ and the conduction loss P_D1-conl of its antiparallel diodes. The conduction losses of switches Q₁/Q₂, P_Q1-conl is expressed as

\(\begin{array}{l} P_{Q_{1}-\mathrm{conl}}=P_{S_{1}-\mathrm{conl}}+P_{D_{1}-\mathrm{conl}} \\ =f_{s} V_{S_{1}} \int_{t_{0}}^{t_{4}} i_{S_{1}} d t+f_{s} V_{D_{1}} \int_{t_{4}}^{t_{5}} i_{D_{1}} d t \\ =f_{s} V_{S_{1}}\left(\frac{I_{0} D T_{h}}{N_{T}}+\frac{V_{i n} C_{r}}{N_{T}^{2}}+\frac{I_{o} \sqrt{L_{r} C_{r}}}{N_{T}^{2}}\right)+f_{s} V_{D_{1}} \frac{I_{o} \sqrt{L_{r} C_{r}}}{N_{T}^{2}} \end{array}\)       (27)

where, V_S1(V_S2) and V_D1(V_D2) are the collector-emitter saturation voltage of switches Q₁/Q₂ and forward voltage of antiparallel diodes D₁/D₂, respectively.

The loss condition of switches Q₃/Q₄ is the same as that of switches Q₁/Q₂.

2) Conduction Loss of the Auxiliary Switches:

The conduction loss P_Q5-conl of switch Q₅ includes the conduction loss P_S5-conl of switches S₅ and the conduction loss P_D5-conl of its antiparallel diode. The conduction losses of switch Q₅, P_Q5-conl is expressed as

\(\begin{array}{l} P_{Q_{5}-\text { conl }}=P_{S_{5}-\text { conl }}+P_{D_{5} -\text { conl }} \\ =f_{s} I_{\mathrm{o}}^{2} R_{D S(o n)} D T_{h}+f_{s} V_{D_{5}} \int_{t_{0}}^{t_{2}} i_{D_{5}} d t \\ =f_{s} I_{\mathrm{o}}^{2} R_{\mathrm{DS}(o n)} D T_{h}+f_{s} V_{D_{5}} I_{\mathrm{o}} D T_{h} \end{array}\)       (28)

where V_D5 is the forward voltage of antiparallel diode D₅ for the auxiliary switch S₅; R_DS(on) is the conduction resistance of the auxiliary switch.

The condition loss of switch Q₆ is the same as that of switch Q₅.

3) Conduction Loss of Diodes:

The conduction loss of rectifier diodes D_R1 (D_R4), P_DR1-conl is expressed as

\(\begin{array}{l} P_{D_{R 1}-c o n l}=f_{s} V_{D_{R 1}} \int_{t_{0}}^{t_{6}} i_{D_{R 1}} d t \\ =f_{s} V_{D_{R 1}}\left[I_{o} D T_{h}+\frac{3 V_{i n} C_{r}}{2 N_{T}}+\frac{(3 \pi-6) I_{o} \sqrt{L_{r} C_{r}}}{4 N_{T}}\right] \end{array}\)       (29)

where V_DR1 is the forward voltage of rectifier diode D_R1.

The total loss of the converter P_total is expressed as follows:

\(P_{\text {total}}=4 P_{Q_{1}-\text {conl}}+2 P_{Q_{5}-\text {conl}}+4 P_{D_{R 1}-\text {conl}}\)       (30)

B. Circulating Current Loss Analysis

Based on the operation principle of the converter, mode 5 is the circulation period (see Fig. 3). According to (27), the circulating current loss is as follows:

\(\begin{array}{l} P_{c i r}=f_{s} V_{D_{1}} \int_{t_{2}}^{t_{3}} i_{D_{1}} d t=\frac{f_{s} I_{o} V_{D_{1}} \sqrt{L_{r} C_{r}}}{N_{T}^{2}} \\ =\left(\frac{f_{s} I_{o} V_{D_{1}}}{2 \pi N_{T}}\right) T_{r} \end{array}\)       (31)

where \(T_{r}=\frac{2 \pi \sqrt{L_{r} C_{r}}}{N_{T}}\) is the resonance cycle.

Based on (11) and (31), we obtain the following.

(1) The square wave current with the amplitude value of the load current flowing through the primary side during circulation period in the conventional phase-shifted full-bridge converter. Compared with it, the circulating current is sinusoidal with the amplitude value of the load current in the proposed converter (see mode 5 in Fig. 3). The effective value of the circulating current is small. Thus, the circulating current loss is relatively smaller.

(2) The magnitude of the circulating current loss is related to the resonant period T_r. It means that the smaller the resonant period is, the smaller the circulating current loss.

VI. PARAMETER DESIGN

A. Design Methodology

Assuming that the input minimum DC voltage is V_inmin , the output maximum voltage is V_omax and the output maximum load current is I_omax. The parameter design of the converter should satisfy the following conditions:

1) Turns Ratio of the Transformer:

To achieve the required output maximum voltage at the lowest input voltage, the turn ratio of the transformer should satisfy the following equation:

\(N_{T}=\frac{V_{i n \min } D_{e f f-\max}}{V_{o \max }+2 V_{D}+V_{L f}}\)       (32)

where V_D is the voltage drop in the secondary rectifier diode, V_Lf is the voltage drop in the output filter inductor.

2) Design of the Auxiliary Resonant Capacitor C_r:

To reduce the turn off the loss of the auxiliary switches, the voltage change rate dv/dt of auxiliary switches during turn-off transient should be smaller than or equal to the setting voltage change rate (dv/dt)_set. Based on (18), the rate can be expressed as follows:

\(\frac{I_{o \max }}{C_{r}} \leq\left(\frac{d v}{d t}\right)_{s e t}\)       (33)

3) Design of the Resonant Inductor L_r:

To reduce the turn off the loss of the primary switches, the current change rate di/dt of primary switches during the turnoff transient period should smaller than or equal to the setting current change rate (di/dt)_set. Based on (19), the rate can be expressed as follows:

\(\frac{V_{i n}}{L_{r}} \leq\left(\frac{d i}{d t}\right)_{s e t}\)       (34)

B. Design Example

The design example of circuit parameters in the prototype is demonstrated by using the numerical example of rating values as follows: input minimum DC voltage V_inmin=740 V, output maximum voltage V_omax=100 V, output maximum load current I_omax=10 A, switching frequency f_S=100 kHz, and rated load resistance R=10 Ω.

Assuming that the voltage change rate of the auxiliary switches (dv/dt)_set=500 V/µs, the current change rate of the primary switches (di/dt)_set=20 A/µs, the maximum effective duty cycle D_eff-max=0.58. The voltage drop of rectifier diode V_D=1.5 V, the voltage drop of the filter inductor V_Lf =0.1 V.

According to (32), the turns ratio of the transformer is N_T=4.16, N_T=4 is chosen. Owing to the voltage change rate of the auxiliary switches (dv/dt)_set=500V/µs, based on (33), C_r≥0.02 μF, and C_r is set as 0.02 μF. Owing to the current change rate of the primary switches (di/dt)_set=20 A/µs, according to (34), L_r≥37 μH, L_r is set as 40 μH.

According to(20), 0.7 μs≤t_δ≤1.42 μs, t_δ=1.4 μs is chosen. Based on (21), t_d≥0.7 μs, t_d=0.7 μs is chosen.

To verify the rationality of the parameter design, based on (23) and (25), D_loss =0.24 and D_td =0.14. D_loss+D_td+D_eff-max=0.96<1. Consequently, the values of parameter design satisfy the demand.

VII. EXPERIMENTAL RESULTS

To verify the validity of the aforementioned analysis, we built a 1 kW prototype. The auxiliary switch uses MOSFET due to its small on-state resistance and low conduction losses. The specifications of the prototype converter are given in Table II.

TABLE II COMPONENTS AND PARAMETERS OF THE PROPOSED CONVERTER

Fig. 9 shows the experimental waveforms of transformer primary voltage v_AB, current i_p, and rectified voltage v_d. Clearly, the primary voltage is smooth and does not have voltage spikes. Owing to the effects of soft-switching technology, the energy stored in the leakage inductance of the transformer is fully absorbed.

Fig. 9. Waveforms of v_AB, i_p, and v_d (I_o=10 A).

Fig. 10 and Fig. 11 show the voltage and current waveforms of the primary switch S₁ and the auxiliary switch S₅ at full load (I_o=10A) and light load (I_o=3A), respectively. From the experimental waveforms, it can be observed that the waveforms of power switches do not have voltage and current spikes. In a wide load range, S₁ turns on with ZCS and turns off with ZVZCS, and S₅ turns on with ZVZCS and turns off with ZVS.

Fig. 10. Switch voltage and current waveforms (I_o=10 A). (a) Switch S₁. (b) Switch S₅.

Fig. 11. Switch voltage and current waveforms (I_o=3 A). (a) Switch S₁. (b) Switch S₅.

Fig. 12 shows the voltage and current waveforms of the rectifier diode D_R2 and D_R4 at full load (I_o=10A) and light load (I_o=3A). It can be seen directly, rectifier diodes can achieve natural switching. And it avoids the reverse recovery problem when the rectifier diode is turned off.

Fig. 12. Voltage and current waveforms of D_R1 and D_R2. (a) Full load (I_o=10 A). (b) Light load (I_o=3 A).

The experimental power loss analysis of the proposed converter and the traditional phase shift full-bridge converter under the rated power are shown in Fig. 13, where the power switch loss includes the switching loss and the conducting loss; the other loss mainly includes the transformer loss and the loss caused by inductors, capacitors, and line resistances. Based on Fig. 13, compared with the traditional phase shift full-bridge converter, the loss caused by the auxiliary switches Q₅ and Q₆ of the proposed converter is 11.44W, but the total loss saved by the primary switches Q₁–Q₄ is 74.45W. The total loss of the proposed converter is 59.87W, and the total loss of the traditional phase shift full-bridge converter is 133.19W. Therefore, the total loss savings is 73.32W in the proposed converter compared with the traditional phase shift full-bridge converter.

Fig. 13. Power loss analysis.

Fig. 14 illustrates the actual power efficiency characteristics of the proposed converter and the traditional phase shift full-bridge converter. Compared with the traditional phase shift full-bridge converter, the overall efficiency of the proposed converter has been appreciably improved, and it is more obvious at the light load. The total actual efficiency of the proposed converter is 94.35% at rated output power 1kW, improving approximately by 6.1%, while improving approximately by 13% at an output power of 300W. However, under power 300W, the proposed converter does not realize complete soft switching. At output power 100W, the efficiency is 81% which is improved approximately by 10%.

Fig. 14. Efficiency curves.

VIII. CONCLUSIONS

A novel ZCS full-bridge soft switching DC–DC converter topology and modulation strategy has been proposed in this paper. The operation principle, the soft switching conditions, and parameter design of the proposed converter have been illustrated in detail. Based on the theoretical analysis and the experimental research on the 1kW prototype, several conclusions have been summarized as follows.

1) The primary switches S₁–S₄ realize ZVZCS turn off and ZCS turn on, and the auxiliary switches S₅ and S₆ realize ZVS turn off and ZVZCS turn on, thereby reducing the switching loss.

2) The rectifier diodes achieve natural switching, and they overcome the reverse recovery problem.

3) The circulating current loss in the proposed converter is smaller than that of the phase shifted full-bridge converter. Furthermore, the smaller the resonant cycle is, the smaller the circulating current loss.

4) The current stress of the primary switches and the voltage stress of the rectifier diodes are the same as the phase-shifted full-bridge converter.

5) The efficiency of the proposed converter is higher than that of the traditional phase shifted full-bridge converter, and this is more obvious in light load. At output power 300 W, the efficiency can be obtained as 88%, which is improved approximately by 13%. At rated power 1kW, the actual high efficiency can be obtained as 94.35%, which is improved approximately by 6.1%.