Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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A 2.4-GHz Dual-Mode CMOS Power Amplifier with a Bypass Structure Using Three-Port Transformer to Improve Efficiency

3-포드 변압기를 이용한 바이패스 구조를 적용하여 효율이 개선된 이중 모드 2.4-GHz CMOS 전력 증폭기

  • Jang, Joseph (School of Electronic Engineering, Soongsil University) ;
  • Yoo, Jinho (School of Electronic Engineering, Soongsil University) ;
  • Lee, Milim (School of Electronic Engineering, Soongsil University) ;
  • Park, Changkun (School of Electronic Engineering, Soongsil University)
  • Received : 2019.05.20
  • Accepted : 2019.05.29
  • Published : 2019.06.30
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Abstract

We propose a 2.4-GHz CMOS power amplifier (PA) with a bypass structure to improve the power-added efficiency (PAE) in the low-power region. The primary winding of the output transformer is split into two parts. One of the primary windings is connected to the output of the power stage for high-power mode. The other primary winding is connected to the output of the driver stage for low-power mode. Operation of the high power mode is similar to conventional PAs. On the other hand, the output power of the driver stage becomes the output power of the overall PA in the low power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. We designed the CMOS PA using a 180-nm RFCMOS process. The measured maximum output power is 27.78 dBm with a PAE of 20.5%. At a measured output power of 16 dBm, the PAE is improved from 2.5% to 12.7%.

본 연구에서는 2.4-GHz CMOS 전력 증폭기의 저 출력 전력 영역에서의 전력 변환 효율을 개선시키기 위한 이중모드 증폭기 구조를 제안하였다. 이를 위하여 출력 정합 회로 및 발룬의 역할을 하는 출력부 변압기의 1차 측을 두 개로 나누고, 그 중 하나는 전력 증폭단의 출력부와, 나머지 하나는 구동 증폭단의 출력부와 연결 되도록 구성하였다. 이를 통하여, 전력 증폭기가 고 출력 전력 영역에서 동작 할 경우, 일반적인 전력 증폭기 동작과 동일하게 동작 하며, 반대로 전력 증폭기가 저출력 전력 영역에서 동작 할 경우, 전력 증폭단은 작동을 하지 않으며, 구동 증폭단의 출력이 전력 증폭기의 최종 출력부로 전달 되도록 구성하였다. 이 경우, 저출력 전력 영역에서는 전력 증폭단에서의 dc 전력소모가 원천적으로 차단되기 때문에 저출력 전력 영역에서의 전력 변환 효율을 개선시킬 수 있다. 제안하는 구조는 180-nm RFCMOS 공정을 통해 설계된 2.4-GHz 전력 증폭기의 측정을 통하여 그 효용성을 검증하였다.

Keywords

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Fig. 1 block diagram of a dual-mode power amplifier:(a) split power stage and (b) bypass structures.

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Fig. 2 Simple schematic of proposed driver stage for bypass structure.

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Fig. 3 Simple schematic of dual-mode CMOS power amplifier using proposed bypass structure.

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Fig. 4 Layout of the designed three-port transformer.

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Fig. 5 Simulation results of ZL,High and ZL,Low.

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Fig. 6 Chip photograph of the designed power amplifier.

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Fig. 7 Measured current consumption according to the output power.

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Fig. 8 Measured gain and PAE according to the output power.

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