Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Design of a DMA Controller for Augmented Reality in Embedded System

증강현실을 위한 임베디드 시스템의 DMA 컨트롤러 설계

  • Jang, Su Yeon (Department of Electronic and Information Engineering, Seoul National University of Science and Technology) ;
  • Oh, Jung Hwan (Department of Electronic Engineering, Seoul National University of Science and Technology) ;
  • Yoon, Young Hyun (Department of Electronic Engineering, Seoul National University of Science and Technology) ;
  • Lee, Seong Mo (Department of Electronic Engineering, Seoul National University of Science and Technology) ;
  • Lee, Seung Eun (Department of Electronic Engineering, Seoul National University of Science and Technology)
  • Received : 2019.05.20
  • Accepted : 2019.06.10
  • Published : 2019.07.31
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Abstract

An Augmented Reality(AR) provides virtual information with a real environment, and the processor needs to access the memory for the AR system. However, the processor has the heavy workload as the technology improvement leads to increase the size of data. We need a specific module to reduce the workload to overcome the limitation. In this paper, we propose a Direct Memory Access(DMA) controller displaying image instead of the processor. We implemented the proposed DMA controller on a Field Programmable Gate Array(FPGA) and demonstrated the functionality of the DMA controller based on an Avalon Memory Mapped(Avalon-MM) interface. Also, the DMA controller is fabricated by using Magnachip/Hynix 0.35um CMOS technology and verified the feasibility of the embedded system.

증강현실은 실제 환경과 함께 가상 정보를 제공하며, 이러한 시스템을 위해 프로세서의 메모리 접근이 요구된다. 하지만 기술 발전에 따라 데이터의 양이 증가함으로써, 프로세서의 작업량 또한 증가하게 된다. 이를 해결하기 위해 임베디드 프로세서의 작업 부하를 감소시킬 수 있는 특정 모듈을 필요로 한다. 본 논문에서는 임베디드 프로세서 대신에 이미지를 출력하는 Direct Memory Acceass(DMA) 컨트롤러를 제안한다. 제안하는 DMA 컨트롤러를 Field Programmable Gate Array(FPGA)에 구현하고 Avalon Memory Mapped(Avalon-MM) 인터페이스를 기반으로 한 DMA 컨트롤러의 기능을 시연한다. 또한, DMA 컨트롤러를 Magnachip/Hynix 0.35um CMOS로 제작하고, 임베디드 시스템의 실현 가능성을 검증한다.

Keywords

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Fig. 1 The structure of the entire system

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Fig. 2 The architecture of the DMA controller

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Fig. 3 The simulation result of the wait_request signal

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Fig. 7 Layout of the DMA controller

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Fig. 8 The front of the proposed DMA controller

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Fig. 9 The back of the proposed DMA controller

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Fig. 4 Wait state initialization of the SDRAM

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Fig. 5 Output of the image data from the DMA Control module

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Fig. 6 The system architecture of the DMA controller

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Cited by

  1. Intellino: Processor for Embedded Artificial Intelligence vol.9, pp.7, 2019, https://doi.org/10.3390/electronics9071169