Journal of Power Electronics

The Korean Institute of Power Electronics (전력전자학회)
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Load and Capacitor Stacking Topologies for DC-DC Step Down Conversion

  • Mace, Jules (Department of Electrical and Computer Engineering, Seoul National University) ;
  • Noh, Gwangyol (Department of Electrical and Computer Engineering, Seoul National University) ;
  • Jeon, Yongjin (Department of Electrical and Computer Engineering, Seoul National University) ;
  • Ha, Jung-Ik (Department of Electrical and Computer Engineering, Seoul National University)
  • Received : 2019.07.31
  • Accepted : 2019.08.26
  • Published : 2019.11.20
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Abstract

This paper presents two voltage domain stacking topologies for powering integrated digital loads such as multiprocessors or 3D integrated circuits. Pairs of loads and capacitors are connected in series to form a stack of voltage domains. The voltage is balanced by switching the position of the capacitors in one case and the position of the loads in the other case. This method makes the voltage regulation robust to large differential load power consumption. The first configuration can be named the load stacking topology. The second configuration can be named the capacitor stacking topology. This paper aims at proposing and comparing these two topologies. Models of both topologies and a switching scheme are presented. The behavior, control scheme, losses and overall performance are analyzed and compared theoretically in simulation and experiments. Experimental results show that the capacitor stacking topology has better performance with a 30% voltage ripple reduction.

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References

  1. R. C. Chu, R. E. Simons, M. J. Ellsworth, R. R. Schmidt, and V. Cozzolino, “Review of cooling technologies for computer products,” IEEE Trans. Device Mater. Rel., Vol. 4, No. 4, pp. 568-585, Dec. 2004. https://doi.org/10.1109/TDMR.2004.840855
  2. K. M. Attia, M. A. El-Hosseini, and H. A. Ali, “Dynamic power management techniques in multi-core architectures: A survey study,” Ain Shams Eng. J., Vol. 8, No. 3, pp. 445-456, Sep. 2017. https://doi.org/10.1016/j.asej.2015.08.010
  3. P. T. Krein, "A discussion of data center power challenges across the system," in 2010 International Conference on Energy Aware Computing, pp. 1-3, 2010.
  4. P. Jain, T. Kim, J. Keane, and C. H. Kim, "A multi-story power delivery technique for 3D integrated circuits," in Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08), pp. 57-62, 2008.
  5. S. Rajapandian, Zheng Xu, and K. L. Shepard, “Implicit DC-DC downconversion through charge-recycling,” IEEE J. Solid-State Circuits, Vol. 40, No. 4, pp. 846-852, Apr. 2005. https://doi.org/10.1109/JSSC.2004.842861
  6. P. S. Shenoy and P. T. Krein, “Differential power processing for DC systems,” IEEE Trans. Power Electron., Vol. 28, No. 4, pp. 1795-1806, Apr. 2013. https://doi.org/10.1109/TPEL.2012.2214402
  7. P. S. Shenoy, S. Zhang, R. A. Abdallah, P. T. Krein, and N. R. Shanbhag, "Overcoming the power wall: Connecting voltage domains in series," in 2011 International Conference on Energy Aware Computing, pp. 1-6, 2011.
  8. P. S. Shenoy, K. A. Kim, B. B. Johnson, and P. T. Krein, “Differential power processing for increased energy production and reliability of photovoltaic systems,” IEEE Trans. Power Electron., Vol. 28, No. 6, pp. 2968-2979, Jun. 2013. https://doi.org/10.1109/TPEL.2012.2211082
  9. S. K. Lee, T. Tong, X. Zhang, D. Brooks, and G. Wei, "A 16-core voltage-stacked system with an integrated switched-capacitor DC-DC converter," in 2015 Symposium on VLSI Circuits (VLSI Circuits), pp. C318-C319, 2015.
  10. H. Le, M. Seeman, S. R. Sanders, V. Sathe, S. Naffziger, and E. Alon, "A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency," in 2010 IEEE International Solid-State Circuits Conference - (ISSCC), pp. 210-211, 2010.
  11. G. Noh and J. Ha, "Analysis and design of four-level flying-capacitor converter in burst mode operation," in 2019 10th International Conference on Power Electronics and ECCE Asia (ICPE 2019 - ECCE Asia), pp. 3129-3134, 2019.
  12. K. Kesarwani, C. Schaef, C. R. Sullivan, and J. T. Stauth, "A multi-level ladder converter supporting vertically-stacked digital voltage domains," in 2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), pp. 429-434, 2013.