Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
권호 표지
DOI QR코드

DOI QR Code

Montgomery Multiplier Supporting Dual-Field Modular Multiplication

듀얼 필드 모듈러 곱셈을 지원하는 몽고메리 곱셈기

  • Kim, Dong-Seong (School of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Shin, Kyung-Wook (School of Electronic Engineering, Kumoh National Institute of Technology)
  • Received : 2020.03.25
  • Accepted : 2020.04.21
  • Published : 2020.06.30
Download PDF
⟨ Previous Next ⟩

Abstract

Modular multiplication is one of the most important arithmetic operations in public-key cryptography such as elliptic curve cryptography (ECC) and RSA, and the performance of modular multiplier is a key factor influencing the performance of public-key cryptographic hardware. An efficient hardware implementation of word-based Montgomery modular multiplication algorithm is described in this paper. Our modular multiplier was designed to support eleven field sizes for prime field GF(p) and binary field GF(2k) as defined by SEC2 standard for ECC, making it suitable for lightweight hardware implementations of ECC processors. The proposed architecture employs pipeline scheme between the partial product generation and addition operation and the modular reduction operation to reduce the clock cycles required to compute modular multiplication by 50%. The hardware operation of our modular multiplier was demonstrated by FPGA verification. When synthesized with a 65-nm CMOS cell library, it was realized with 33,635 gate equivalents, and the maximum operating clock frequency was estimated at 147 MHz.

모듈러 곱셈은 타원곡선 암호 (elliptic curve cryptography; ECC), RSA 등의 공개키 암호에서 중요하게 사용되는 산술연산 중 하나이며, 모듈러 곱셈기의 성능은 공개키 암호 하드웨어의 성능에 큰 영향을 미치는 핵심 요소가 된다. 본 논문에서는 워드기반 몽고메리 모듈러 곱셈 알고리듬의 효율적인 하드웨어 구현에 대해 기술한다. 본 논문의 모듈러 곱셈기는 SEC2 ECC 표준에 정의된 소수체 GF(p)와 이진체 GF(2k) 상의 11가지 필드 크기를 지원하여 타원곡선 암호 프로세서의 경량 하드웨어 구현에 적합하도록 설계되었다. 제안된 곱셈기 구조는 부분곱 생성 및 가산 연산과 모듈러 축약 연산이 파이프라인 방식으로 처리하며, 곱셈 연산에 소요되는 클록 사이클 수를 약 50% 줄였다. 설계된 모듈러 곱셈기를 FPGA 디바이스에 구현하여 하드웨어 동작을 검증하였으며, 65-nm CMOS 표준셀로 합성한 결과 33,635개의 등가 게이트로 구현되었고, 최대 동작 클록 주파수는 147 MHz로 추정되었다.

Keywords

References

  1. Z. Liu, D. Liu, and X. Zou, "An Efficient and Flexible Hardware Implementation of the Dual-Field Elliptic Curve Cryptographic Processor," IEEE Transactions on Industrial Electronics, vol. 64, no. 3, pp. 2353-2362, Mar. 2017. https://doi.org/10.1109/TIE.2016.2625241
  2. C. A. Lara-Nino, A. Diaz-Perez, and M. Morales-Sandoval, "Elliptic Curve Lightweight Cryptography: A Survey," in IEEE Access, vol. 6, pp. 72514-72550, 2018. https://doi.org/10.1109/access.2018.2881444
  3. N. Thampi, and M. E. Jose, "Montgomery Multiplier for Faster Cryptosystems," Procedia Technology, vol. 25, pp. 392-398, 2016. https://doi.org/10.1016/j.protcy.2016.08.123
  4. D. B. Roy, and D. Mukhopadhyay, "High-Speed Implementation of ECC Scalar Multiplication in GF(p) for Generic Montgomery Curves," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 7, pp. 1587-1600, July 2019. https://doi.org/10.1109/TVLSI.2019.2905899
  5. P. L. Montgomery, "Modular multiplication without trial division," Mathematics of computation, vol. 44, no. 170, pp. 519-521, Apr. 1985. https://doi.org/10.1090/S0025-5718-1985-0777282-X
  6. A. Nadjia, and A. Mohamed, "High Throughput Parallel Montgomery Modular Exponentiation on FPGA," in Proceeding of the 9th International Symposium on Design and Test, Algiers, pp. 225-230, 2014.
  7. A. Rezai, and P. Keshavarzi, "High-throughput Modular Multiplication and Exponentiation Algorithms using Multibit-scan-multibit-shift Technique," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 9, pp. 1710-1719, Sep. 2015. https://doi.org/10.1109/TVLSI.2014.2355854
  8. C. K. Koc, T. Acar, and B. S. Kaliski, "Analyzing and Comparing Montgomery Multiplication Algorithms," IEEE Micro, vol. 16, no. 3, pp. 26-33, Jun. 1996. https://doi.org/10.1109/40.502403
  9. S. H. Lee, "A Lightweight ECC Processor Supporting Dual Field Elliptic Curves of GF(p) and GF(2m)," Master's Thesis, Kumoh National Institute of Technology, Jun. 2019.
  10. D. S. Kim, and K. W. Shin, "A Design of Montgomery Modular Multiplier supporting Prime Field and Binary Field," Proceedings of 2019 1st Conference of the Institute of Electronics and Information Engineers, vol. 42, no. 1, pp. 54-55, Jeju, 2019.
  11. SEC 2. "Elliptic Curve Cryptography," Standards for Efficient Cryptography Group, Sep. 2000.
  12. R. Verna, M. Duttam, and R. Vig, "FPGA Implementation of Modified Montgomery for RSA Cryptosystem," International Journal of Computer Science and Telecommunication, vol. 4, no. 1, pp. 42-46. Jan. 2013.
  13. Y. Yang, C. Wu, Z. Li, and J. Yang "Efficient FPGA Implementation of Modular Multiplication based on Montgomery Algorithm," Microprocessors and Microsystems, vol. 47, pp. 209-215, Apr. 2016. https://doi.org/10.1016/j.micpro.2016.07.008
  14. S. Erdem, T. Yamk, and A. Celebi, "A General Digit-Serial Architecture for Montgomery Modular Multiplication," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 5, pp. 1658-1668. May 2017. https://doi.org/10.1109/TVLSI.2017.2652979