Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Acceleration of ECC Computation for Robust Massive Data Reception under GPU-based Embedded Systems

GPU 기반 임베디드 시스템에서 대용량 데이터의 안정적 수신을 위한 ECC 연산의 가속화

  • Kwon, Jisu (School of Electronic Engineering, Kyungpook National University) ;
  • Park, Daejin (School of Electronic Engineering, Kyungpook National University)
  • Received : 2020.04.27
  • Accepted : 2020.05.12
  • Published : 2020.07.31
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Abstract

Recently, as the size of data used in an embedded system increases, the need for an ECC decoding operation to robustly receive a massive data is emphasized. In this paper, we propose a method to accelerate the execution of computations that derive syndrome vectors when ECC decoding is performed using Hamming code in an embedded system with a built-in GPU. The proposed acceleration method uses the matrix-vector multiplication of the decoding operation using the CSR format, one of the data structures representing sparse matrix, and is performed in parallel in the CUDA kernel of the GPU. We evaluated the proposed method using a target embedded board with a GPU, and the result shows that the execution time is reduced when ECC decoding operation accelerated based on the GPU than used only CPU.

최근 임베디드 시스템에서 사용되는 데이터의 크기가 증가함에 따라, 대용량의 데이터를 안전하게 수신하기 위한 ECC (Error Correction Code) 복호화 연산의 필요성이 강조되고 있다. 본 논문에서는 GPU가 내장된 임베디드 시스템에서 해밍 코드를 사용하여 ECC 복호화를 할 때, 신드롬 벡터를 계산하는 연산의 수행을 가속할 방법을 제안한다. 제안하는 가속화 방법은, 복호화 연산의 행렬-벡터 곱셈이 희소 행렬을 나타내는 자료 구조 중 하나인 CSR (Compressed Sparse Row) 형식을 사용하고, GPU의 CUDA 커널에서 병렬적으로 수행되도록 한다. 본 논문에서는 GPU가 내장된 실제 임베디드 보드를 사용하여 제안하는 방법을 검증하였고, 결과는 GPU 기반으로 가속된 ECC 복호화 연산이 CPU만을 사용한 경우에 비하여 수행 시간이 감소하는 것을 보여준다.

Keywords

References

  1. V. S. Chua, J. Z. Esquivel, A. S. Paul, T. Techathamnukool, C. F. Fajardo, N. Jain, O. Tickoo, R. Iyer, "Visual IoT: Ultra-Low-Power Processing Architectures and Implications," IEEE Micro, vol. 37, no. 6, pp. 52-61, November/December 2017. https://doi.org/10.1109/MM.2017.4241343
  2. D. H. Hwang and K. S. Jang, "Fast Hand-Gesture Recognition Algorithm For Embedded System," Journal of the Korea Institute of Information and Communication Engineering, vol. 21, no. 7, pp. 1349-1354, Jul. 2017. https://doi.org/10.6109/jkiice.2017.21.7.1349
  3. S. Y. Cho, "Design and Implementation of Fail Recovery Process on Highly-Reliable Embedded Linux System," Journal of Security Engineering, vol.11, no.2, pp. 89-100, Feb. 2014. https://doi.org/10.14257/jse.2014.02.02
  4. R. Motwani, Z. Kwok, S. Nelson, "Low density parity check (LDPC) codes and the need for stronger ECC," Flash Memory Summit, 2011.
  5. K. Sripimanwat, Turbo Code Applications, Vol. 1. Dordrecht: Springer, 2005.
  6. W. Liu, J. Rho, W. Sung, "Low-power high-throughput BCH error correction VLSI design for multi-level cell NAND flash memories," in 2006 IEEE Workshop on Signal Processing Systems Design and Implementation. pp. 303-308, 2006.
  7. S. Keskin and T. Kocak, "GPU accelerated gigabit level BCH and LDPC concatenated coding system," in 2017 IEEE High Performance Extreme Computing Conference (HPEC), Waltham: MA, pp. 1-4, 2017.
  8. A. K. Subbiah and T. Ogunfunmi, "Memory-efficient Error Correction Scheme for Flash Memories using GPU," in 2018 IEEE International Workshop on Signal Processing Systems (SiPS), Cape Town, pp. 118-122, 2018.
  9. S. Kim, J. Cho and D. Park, "Moving-Target Position Estimation Using GPU-Based Particle Filter for IoT Sensing Applications," Applied Sciences, vol. 7, no. 11, pp. 1152, Nov. 2017. https://doi.org/10.3390/app7111152
  10. S. Kim, J. Cho and D. Park, "Accelerated DEVS Simulation Using Collaborative Computation on Multi-Cores and GPUs for Fire-Spreading IoT Sensing Applications," Applied Sciences, vol. 8, no. 9, pp. 1466, Aug. 2018. https://doi.org/10.3390/app8091466
  11. A. K. Subbiah and T. Ogunfunmi, "Three-bit fast error corrector for BCH codes on GPUs," in 2019 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas: NV, pp. 1-4, 2019.
  12. H. L. Kalter, C. H. Stapper, J. E. Barth, J. DiLorenzo, C. E. Drake, J. A. Fifield, G. A. Kelly, S. C. Lewis, W. B. van der Hoeven, J. A. Yankosky, "A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC," IEEE Journal of Solid-State Circuits, vol. 25, no. 5, pp. 1118-1128, Oct. 1990. https://doi.org/10.1109/4.62132
  13. T. Tanzawa, T. Tanaka, K. Takeuchi, R. Shirota, S. Aritome, H. Watanabe, G. Hemink, K. Shimizu, S. Sato, Y. Takeuchi, K. Ohuchi, "A compact on-chip ECC for low cost flash memories," IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. 662-669, May 1997. https://doi.org/10.1109/4.568829
  14. K. Dang and X. Tran, "Parity-Based ECC and Mechanism for Detecting and Correcting Soft Errors in On-Chip Communication," in 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Hanoi, pp. 154-161, 2018.