한국컴퓨터정보학회논문지 (Journal of the Korea Society of Computer and Information)

  • 제25권3호
  • /
  • Pages.1-9
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  • 2020
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  • 1598-849X(pISSN)
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  • 2383-9945(eISSN)
한국컴퓨터정보학회 (Korean Society of Computer Information)
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Dead Block-Aware Adaptive Write Scheme for MLC STT-MRAM Caches

  • Hong, Seokin (School of Computer Science and Engineering, Kyungpook National University)
  • 투고 : 2020.02.11
  • 심사 : 2020.03.03
  • 발행 : 2020.03.31
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 MLC STT-MRAM 캐시 메모리의 쓰기 동작 성능을 향상시킬 수 있는 효율적인 쓰기 기법을 제안한다. 제안하는 기법의 핵심 아이디어는 MLC STT-MRAM에 저장된 캐시 블록이 데드 블록 (Dead block)일 경우 쓰기 동작을 빠르게 수행하는 것이다. 이러한 빠른 쓰기 동작은 MLC STT-MRAM에 저장된 캐시 블록을 제거할 수 있지만, 제거된 블록이 앞으로 사용되지 않는 데드 블록일 경우에는 시스템 성능에 미치는 영향이 매우 작다. 메모리 시뮬레이터를 사용한 실험 평가를 통해 본 논문에서 제안하는 쓰기 기법이 MLC STT-MRAM 캐시의 성능을 평균 17% 향상시킬 수 있음을 보인다.

In this paper, we propose an efficient adaptive write scheme that improves the performance of write operation in MLC STT-MRAM caches. The key idea of the proposed scheme is to perform the write operation fast if the target MLC STT-MRAM cells contain a dead block. Even if the fast write operation on the MLC STT-MRAM evicts a cache block from the MLC STT-MRAM cells, its performance impact is low if the evicted block is a dead block which is not used in the future. Through experimental evaluation with a memory simulator, we show that the proposed adaptive write scheme improves the performance of the MLC STT-MRAM caches by 17% on average.

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참고문헌

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