한국컴퓨터정보학회논문지 (Journal of the Korea Society of Computer and Information)

  • 제25권4호
  • /
  • Pages.1-9
  • /
  • 2020
  • /
  • 1598-849X(pISSN)
  • /
  • 2383-9945(eISSN)
한국컴퓨터정보학회 (Korean Society of Computer Information)
권호 표지
DOI QR코드

DOI QR Code

Dynamic Rank Subsetting with Data Compression

  • Hong, Seokin (School of Computer Science and Engineering, Kyungpook National University)
  • 투고 : 2020.03.23
  • 심사 : 2020.04.16
  • 발행 : 2020.04.29
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 데이터 압축을 통해 메모리 시스템의 에너지 효율 및 성능을 향상시키는 동적랭크 서브세팅 기법 (Dynamic Rank Subsetting, DRAS)을 제안한다. DRAS 기법은 하나의 메모리 랭크 (Rank)를 두 개의 서브랭크 (Sub-rank)로 동작되도록 하여, 데이터가 절반 크기로 압축될 경우 압축된 데이터를 하나의 서브랭크에만 저장한다. 이를 통해 DRAS 기법은 압축된 데이터에 대한 읽기 및 쓰기 동작의 메모리 대역폭을 두 배로 높일 수 있고, 동적 전력 소모도 절반으로 감소시킬 수 있다. 만약 데이터가 절반 크기로 압축되지 않는다면 기존 메모리 시스템에서와 같이 데이터를 두 서브랭크에 저장한다. 따라서 DRAS 기법은 데이터가 압축되지 않는 경우에 대해서는 기존 메모리 시스템 수준의 메모리 대역폭과 전력 효율성을 보장한다. 메모리 시뮬레이터를 사용한 실험 평가를 통해 DRAS 기법이 컴퓨터 시스템 성능을 평균 12% 향상시키고 메모리 시스템의 전력소모를 평균 24% 감소시킬 수 있음을 보인다.

In this paper, we propose Dynamic Rank Subsetting (DRAS) technique that enhances the energy-efficiency and the performance of memory system through the data compression. The goal of this technique is to enable a partial chip access by storing data in a compressed format within a subset of DRAM chips. To this end, a memory rank is dynamically configured to two independent sub-ranks. When writing a data block, it is compressed with a data compression algorithm and stored in one of the two sub-ranks. To service a memory request for the compressed data, only a sub-rank is accessed, whereas, for a memory request for the uncompressed data, two sub-ranks are accessed as done in the conventional memory systems. Since DRAS technique requires minimal hardware modification, it can be used in the conventional memory systems with low hardware overheads. Through experimental evaluation with a memory simulator, we show that the proposed technique improves the performance of the memory system by 12% on average and reduces the power consumption of memory system by 24% on average.

키워드

참고문헌

  1. Justin Meza, Mehul A. Shah, Parthasarathy Ranganathan, Mike Fitzner, and Judson Veazey, "Tracking the power in an enterprise decision support system," Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design, pp. 261-266, New York, USA, 2009. DOI: 10.1145/1594233.1594295
  2. H. David, E. Gorbatov, U. R. Hanebutte, R. Khanna and C. Le, "RAPL: Memory power estimation and capping," Proceedings of the 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design, pp. 189-194, Austin, USA, 2010. DOI: 10.1145/1840845.1840883
  3. Hongzhong Zheng, Jiang Lin, Zhao Zhang, Eugene Gorbatov, Howard David, and Zhichun Zhu, "Mini-rank: Adaptive DRAM architecture for improving memory power efficiency," Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture, pp. 210-221, USA, 2008. DOI: 10.1109/MICRO.2008.4771792
  4. Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, and Norman P. Jouppi, "Rethinking DRAM design and organization for energy-constrained multi-cores," Proceedings of the 37th annual international symposium on Computer architecture , pp. 175-186, New York, USA, 2010. DOI: 10.1145/1815961.1815983
  5. J. H. Ahn, N. P. Jouppi, C. Kozyrakis, J. Leverich and R. S. Schreiber, "Future scaling of processor-memory interfaces," Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, pp. 1-12, Portland, OR, 2009. DOI: 10.1145/1654059.1654102
  6. J. H. Ahn, J. Leverich, R. Schreiber and N. P. Jouppi, "Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs," IEEE Computer Architecture Letters, vol. 8, no. 1, pp. 5-8, Jan. 2009. DOI: 10.1109/L-CA.2008.13
  7. A. Shafiee, M. Taassori, R. Balasubramonian and A. Davis, "MemZip: Exploring unconventional benefits from memory compression," 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), pp. 638-649, Orlando, FL, 2014. DOI: 10.1109/HPCA.2014.6835972
  8. Gennady Pekhimenko, Vivek Seshadri, Yoongu Kim, Hongyi Xin, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, and Todd C. Mowry, "Linearly compressed pages: a low-complexity, low-latency main memory compression framework," Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 172-184, New York, USA, 2013. DOI:10.1145/2540708.2540724
  9. G. Pekhimenko, V. Seshadri, O. Mutlu, M. A. Kozuch, P. B. Gibbons and T. C. Mowry, "Base-delta-immediate compression: Practical data compression for on-chip caches," 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 377-388, Minneapolis, MN, 2012. DOI: 10.1145/2370816.2370870
  10. A. R. Alameldeen and D. A. Wood, "Frequent pattern compression: A significance-based compression scheme for l2 caches," Dept. Comp. Scie., Univ. Wisconsin-Madison, Tech. Rep, vol. 1500, 2004.
  11. N. Chatterjee et al., USIMM: The Utah Simulated Memory Module, tech. report UUCS-12-002, Univ. of Utah, 2012.
  12. Vinson Young, Prashant J. Nair, and Moinuddin K. Qureshi, "DICE: Compressing DRAM Caches for Bandwidth and Capacity," Proceedings of the 44th Annual International Symposium on Computer Architecture (ISCA '17), pp. 627-638, New York, USA. DOI: 10.1145/3079856.3080243
  13. V. Young, S. Kariyappa, and M. Qureshi, "Enabling Transparent Memory-Compression for Commodity Memory Systems," Proceedings of 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 570-581, Washington, USA, 2019. DOI: 10.1109/HPCA.2019.00010
  14. Seokin Hong, Bulent Abali, Alper Buyuktosunoglu, Michael B. Healy, and Prashant J. Nair, "Touche: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads," Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO '52). Association for Computing Machinery, pp. 453-465, New York, USA, 2019. DOI:10.1145/3352460.3358281
  15. Seokin Hong, Prashant J. Nair, Bulent Abali, Alper Buyuktosunoglu, Kyu-Hyoun Kim, and Michael B. Healy, "Attache: towards ideal memory compression by mitigating metadata bandwidth overheads," Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-51), pp. 326-338, 2018. DOI:10.1109/MICRO.2018.00034
  16. Somayeh Sardashti and David A. Wood. 2017. Could Compression Be of General Use? Evaluating Memory Compression Across Domains. ACM Trans. Archit. Code Optim. 14, 4, Article 44, 24 pages, 2017. DOI: 10.1145/3138805