ETRI Journal

  • 제42권4호
  • /
  • Pages.491-504
  • /
  • 2020
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  • 1225-6463(pISSN)
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  • 2233-7326(eISSN)
한국전자통신연구원 (Electronics and Telecommunications Research Institute)
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AB9: A neural processor for inference acceleration

  • Cho, Yong Cheol Peter (AI Processor Research Team, AI SoC Research Department, Electronics and Telecommunications Research Institute) ;
  • Chung, Jaehoon (AI Processor Research Team, AI SoC Research Department, Electronics and Telecommunications Research Institute) ;
  • Yang, Jeongmin (AI Processor Research Team, AI SoC Research Department, Electronics and Telecommunications Research Institute) ;
  • Lyuh, Chun-Gi (AI Processor Research Team, AI SoC Research Department, Electronics and Telecommunications Research Institute) ;
  • Kim, HyunMi (AI Processor Research Team, AI SoC Research Department, Electronics and Telecommunications Research Institute) ;
  • Kim, Chan (AI Processor Research Team, AI SoC Research Department, Electronics and Telecommunications Research Institute) ;
  • Ham, Je-seok (AI Processor Research Team, AI SoC Research Department, Electronics and Telecommunications Research Institute) ;
  • Choi, Minseok (AI Processor Research Team, AI SoC Research Department, Electronics and Telecommunications Research Institute) ;
  • Shin, Kyoungseon (AI Processor Research Team, AI SoC Research Department, Electronics and Telecommunications Research Institute) ;
  • Han, Jinho (AI Processor Research Team, AI SoC Research Department, Electronics and Telecommunications Research Institute) ;
  • Kwon, Youngsu (AI Processor Research Team, AI SoC Research Department, Electronics and Telecommunications Research Institute)
  • 투고 : 2020.04.16
  • 심사 : 2020.07.02
  • 발행 : 2020.08.18
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초록

We present AB9, a neural processor for inference acceleration. AB9 consists of a systolic tensor core (STC) neural network accelerator designed to accelerate artificial intelligence applications by exploiting the data reuse and parallelism characteristics inherent in neural networks while providing fast access to large on-chip memory. Complementing the hardware is an intuitive and user-friendly development environment that includes a simulator and an implementation flow that provides a high degree of programmability with a short development time. Along with a 40-TFLOP STC that includes 32k arithmetic units and over 36 MB of on-chip SRAM, our baseline implementation of AB9 consists of a 1-GHz quad-core setup with other various industry-standard peripheral intellectual properties. The acceleration performance and power efficiency were evaluated using YOLOv2, and the results show that AB9 has superior performance and power efficiency to that of a general-purpose graphics processing unit implementation. AB9 has been taped out in the TSMC 28-nm process with a chip size of 17 × 23 ㎟. Delivery is expected later this year.

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참고문헌

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피인용 문헌

  1. 인공지능 프로세서 컴파일러 개발 동향 vol.36, pp.2, 2020, https://doi.org/10.22648/etri.2021.j.360204