Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Low Power ADC Design for Mixed Signal Convolutional Neural Network Accelerator

혼성신호 컨볼루션 뉴럴 네트워크 가속기를 위한 저전력 ADC설계

  • Lee, Jung Yeon (Mixed Signal Integrated System Lab, ChungBuk National University) ;
  • Asghar, Malik Summair (Mixed Signal Integrated System Lab, ChungBuk National University) ;
  • Arslan, Saad (Department of Electrical and Computer Engineering, COMSATS University Islamabad) ;
  • Kim, HyungWon (Mixed Signal Integrated System Lab, ChungBuk National University)
  • Received : 2021.08.25
  • Accepted : 2021.09.29
  • Published : 2021.11.30
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Abstract

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛2, power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.

본 논문은 저전력 뉴럴 네트워크 가속기 SOC를 위한 아날로그 Convolution Filter용 저전력 초소형 ADC 회로 및 칩 설계 기술을 소개한다. 대부분의 딥러닝의 학습과 추론을 할 수 있는 Convolution neural network accelerator는 디지털회로로 구현되고 있다. 이들은 수많은 곱셈기 및 덧셈기를 병렬 구조로 구현하며, 기존의 복잡한 곱셉기와 덧셈기의 디지털 구현 방식은 높은 전력소모와 큰 면적을 요구하는 문제점을 가지고 있다. 이 한계점을 극복하고자 본 연구는 디지털 Convolution filter circuit을 Analog multiplier와 Accumulator, ADC로 구성된 Analog Convolution Filter로 대체한다. 본 논문에서는 최소의 칩면적와 전력소모로 Analog Accumulator의 아날로그 결과 신호를 디지털 Feature 데이터로 변환하는 8-bit SAR ADC를 제안한다. 제안하는 ADC는 Capacitor Array의 모든 Capacitor branch에 Split capacitor를 삽입하여 모든 branch의 Capacitor 크기가 균등하게 Unit capacitor가 되도록 설계하여 칩면적을 최소화 한다. 또한 초소형 unit capacitor의 Voltage-dependent capacitance variation 문제점을 제거하기 Flipped Dual-Capacitor 회로를 제안한다. 제안하는 ADC를 TSMC CMOS 65nm 공정을 이용하여 설계하였으며, 전체 chip size는 1355.7㎛2, Power consumption은 2.6㎼, SNDR은 44.19dB, ENOB는 7.04bit의 성능을 달성하였다.

Keywords

Acknowledgement

This study was conducted as a result of the research result of the Grand ICT Research Center support project of the Ministry of Science and ICT and the Institute for Information & communication Technology Planning & evaluation(IITP). (IITP-2020-0-01462)

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