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Telemetry Standard 106-17 LDPC Decoder Design Using HLS

HLS를 이용한 텔레메트리 표준 106-17 LDPC 복호기 설계

  • Received : 2020.10.27
  • Accepted : 2021.02.23
  • Published : 2021.04.01

Abstract

By using HLS when developing a communication system FPGA, HDL code can be automatically generated from a little modified C/C++ source code used for performance verification, which has the advantage of shortening the development period. In this paper, a method of designing a telemetry standard 106-17 LDPC decoder in C language is proposed using Xilinx's Vivado HLS, and by synthesizing Spartan-7 and Kintex-7 as target devices, throughput and FPGA utilization rate was compared.

통신 시스템 FPGA 개발 시 HLS를 이용하면 성능 검증용 C/C++ 소스 코드를 일부 수정하여 자동으로 HDL 코드를 생성할 수 있으므로 개발 기간을 단축할 수 있는 장점이 있다. 본 논문에서는 텔레메트리 표준 106-17 LDPC 복호기를 Xilinx사의 Vivado HLS를 이용하여 C언어로 설계하는 방법을 제시하였고, Spartan-7와 Kintex-7 디바이스를 타겟으로 합성하여 throughput과 FPGA 이용률을 비교하였다.

Keywords

References

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