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CMOS Binary Image Sensor Using Double-Tail Comparator with High-Speed and Low-Power Consumption

  • Kwen, Hyeunwoo (School of Electronic and Electrical Engineering, Kyungpook National University) ;
  • Jang, Junyoung (School of Electronic and Electrical Engineering, Kyungpook National University) ;
  • Choi, Pyung (School of Electronic and Electrical Engineering, Kyungpook National University) ;
  • Shin, Jang-Kyoo (School of Electronic and Electrical Engineering, Kyungpook National University)
  • Received : 2021.03.22
  • Accepted : 2021.03.30
  • Published : 2021.03.31

Abstract

In this paper, we propose a high-speed, low-power complementary metal-oxide semiconductor (CMOS) binary image sensor featuring a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector based on a double-tail comparator. The GBT photodetector forms a structure in which the floating gate (n+ polysilicon) and body of the PMOSFET are tied, and amplifies the photocurrent generated by incident light. The double-tail comparator compares the output signal of a pixel against a reference voltage and returns a binary signal, and it exhibits improved power consumption and processing speed compared with those of a conventional two-stage comparator. The proposed sensor has the advantages of a high signal processing speed and low power consumption. The proposed CMOS binary image sensor was designed and fabricated using a standard 0.18 ㎛ CMOS process.

Keywords

References

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