The Journal of the Korea institute of electronic communication sciences (한국전자통신학회논문지)

Korea Institute of Electronic Communication Science (한국전자통신학회)
권호 표지
DOI QR코드

DOI QR Code

Design of ZQ Calibration Circuit using Time domain Comparator

시간영역 비교기를 이용한 ZQ 보정회로 설계

  • 이상훈 (서울과학기술대학교) ;
  • 이원영 (서울과학기술대학교 전자IT미디어공학과)
  • Received : 2021.04.12
  • Accepted : 2021.06.17
  • Published : 2021.06.30
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, a ZQ calibration using a time domain comparator is proposed. The proposed comparator is designed based on VCO, and an additional clock generator is used to reduce power consumption. By using the proposed comparator, the reference voltage and the PAD voltage were compared with a low 1 LSB voltage, so that the additional offset cancelation process could be omitted. The proposed time domain comparator-based ZQ calibration circuit was designed with a 65nm CMOS process with 1.05V and 0.5V supply voltages. The proposed clock generator reduces power consumption by 37% compared to a single time domain comparator, and the proposed ZQ calibration increases the mask margin by up to 67.4%.

본 논문에서는 시간영역 비교기를 응용한 ZQ 보정회로를 제안한다. 제안하는 비교기는 VCO기반으로 설계되었으며 전력소모를 감소시키기 위해 추가적인 클록 발생기를 사용하였다. 제안한 비교기를 사용하여 참조 전압과 PAD 전압을 낮은 1 LSB 전압 단위로 비교하여 추가적인 오프셋 보정과정을 생략할 수 있었다. 제안하는 시간영역 비교기 기반의 ZQ 보정회로는 1.05 V 및 0.5 V 공급전압의 65 nm CMOS공정으로 설계되었다. 제안한 클록 발생기를 통해 단일 시간영역 비교기 대비 37 %의 전력소모가 감소하였으며 제안하는 ZQ 보정 회로를 통해 최대 67.4 %의 mask margin을 증가시켰다.

Keywords

Acknowledgement

이 성과는 2021년도 정부(과학기술정보통신부)의 재원으로 한국연구재단의 지원을 받아 수행된 연구임(No. NRF-2020R1C1C1011773). 본 연구는 IDEC에서 EDA Tool를 지원받아 수행하였습니다.

References

  1. C. Jung and W. Lee, "A Low Jitter Delay-Locked Loop for Local Clock Skew Compensation," J. of the Korea Institute of Electronic Communication Science, vol. 14, no. 2, 2019, pp. 309-316. https://doi.org/10.13067/JKIECS.2019.14.2.309
  2. W. Lee, "An Adaptive Equalizer with the Digitally Controlled Active Variable Capacitor," J. of the Korea Institute of Electronic Communication Science, vol. 11, no. 11, 2016, pp. 1053-1060. https://doi.org/10.13067/JKIECS.2016.11.11.1053
  3. W. Lee and G. Lee, "A Low Power Voltage Controlled Oscillator with Bandwidth Extension Scheme," J. of the Korea Institute of Electronic Communication Science, vol. 16, no. 1, 2021, pp. 69-74. https://doi.org/10.13067/JKIECS.2021.16.1.69
  4. C. Yoo, K. Kyung, H. Lee, J. Chai, N. Heo, D. Lee, and C. Kim, "A 1.8-V 700-Mb/s/pin 512-Mb DDR-II SDRAM with on-die termination and off-chip driver calibration," IEEE J. Solid-State Circuits, vol. 39, no. 6, 2004, pp. 941-951. https://doi.org/10.1109/JSSC.2004.827806
  5. Z. Ding, X. Zhou, and Q. Li, "A 0.5-1.1-V adaptive SAR ADC utilizing the oscillation-cycle information of a VCO-based comparator," IEEE J. Solid-State Circuits, vol. 54, no. 4, 2019, pp. 968-977. https://doi.org/10.1109/JSSC.2018.2885554
  6. S. Lee, S. Park, and J. Sim, "A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC with a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface," IEEE J. Solid-State Circuits, vol. 46, no. 3, 2011, pp. 651-659. https://doi.org/10.1109/JSSC.2010.2102590
  7. JEDEC Standard LPDDR5 SDRAM specification, JESD209-5A, Dec. 2018.