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A Study on Extension of One-bit of the Parallel Interface type Digital-to-Analog Conversion Circuit

병렬 인터페이스형 디지털/아날로그 변환회로의 1개 비트 확장에 관한 연구

  • Kwon, Sung-Yeol (Department of Electrical Engineering, PuKyong National Univ.) ;
  • Lee, Hyun-Chang (Division of Information & Telecommunications, KongJu National Univ.)
  • Received : 2021.06.20
  • Accepted : 2021.08.20
  • Published : 2021.08.28

Abstract

In this paper, a method of extending 1 bit by adding an external device to a parallel interface type Digital-to-Analog conversion(D/A C) circuit is presented. To do this, the principle of the D/A C circuit was examined, and the problems that occur when extending one bit by adding individual devices were analyzed, and a bit extension method of the D/A devices using an OP-Amp. circuit was presented. As the proposed method uses the high-precision characteristics of the OP-Amp., even if an error occurs in the device, only the overall size of the output waveform is affected, and the voltage reversal phenomenon that occurs between each bit does not occur. In order to confirm the effect of the proposed method, an experimental circuit was constructed and the absolute voltage of the output and the relative error were measured. As a result, a voltage error of 0.0756% appeared, confirming that the 0.195% requirement for one bit expansion by adding individual devices was sufficiently satisfied.

본 논문에서는 병렬 인터페이스형 디지털/아날로그 변환회로에 외부 소자를 추가해 1개 비트를 확장하는 방법을 제시했다. 이를 위해 디지털/아날로그 변환회로의 원리를 살펴보고 개별 소자를 추가해 1개 비트를 확장하는 경우에 발생되는 문제점을 분석했으며, 연산증폭기 회로를 이용한 디지털/아날로그 소자의 비트 확장 방법을 제시했다. 제시한 방법은 연산증폭기의 고정밀도 특성을 이용함에 따라 소자에 오차가 발생하더라도 출력파형의 전체적인 크기에만 영향을 미치고 각 비트 사이에서 발생하는 전압역전 현상은 발생하지 않는 특징을 지닌다. 제시한 방법의 효과를 확인하기 위해 실험회로를 구성해 출력의 절대전압 측정과 상대적 오차 측정을 실시한 결과 0.0756%의 전압오차가 나타남으로서 개별소자 추가에 의해 1개 비트 확장 시 요건인 0.195%를 충분히 충족함을 확인했다.

Keywords

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