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A Digital Phase-locked Loop design based on Minimum Variance Finite Impulse Response Filter with Optimal Horizon Size

최적의 측정값 구간의 길이를 갖는 최소 공분산 유한 임펄스 응답 필터 기반 디지털 위상 고정 루프 설계

  • 유성현 (조선대학교 전자공학부) ;
  • 배동성 (상명대학교 소프트웨어학과) ;
  • 최현덕 (전남대학교 ICT융합시스템공학과)
  • Received : 2021.07.14
  • Accepted : 2021.08.17
  • Published : 2021.08.31

Abstract

The digital phase-locked loops(DPLL) is a circuit used for phase synchronization and has been generally used in various fields such as communication and circuit fields. State estimators are used to design digital phase-locked loops, and infinite impulse response state estimators such as the well-known Kalman filter have been used. In general, the performance of the infinite impulse response state estimator-based digital phase-locked loop is excellent, but a sudden performance degradation may occur in unexpected situations such as inaccuracy of initial value, model error, and disturbance. In this paper, we propose a minimum variance finite impulse response filter with optimal horizon for designing a new digital phase-locked loop. A numerical method is introduced to obtain the measured value interval length, which is an important parameter of the proposed finite impulse response filter, and to obtain a gain, the covariance matrix of the error is set as a cost function, and a linear matrix inequality is used to minimize it. In order to verify the superiority and robustness of the proposed digital phase-locked loop, a simulation was performed for comparison and analysis with the existing method in a situation where noise information was inaccurate.

디지털 위상 고정 루프는 위상 동기화를 위해 사용되는 회로로 일반적으로 통신, 회로분야 등 다양한 분야에서 사용된다. 디지털 위상 고정 루프를 설계 시 상태추정기를 사용하는 경우 보통 칼만 필터와 같은 무한 임펄스 응답 상태추정기를 활용해왔다. 일반적으로 무한 임펄스 응답 상태추정기 기반 디지털 위상 고정 루프의 성능은 우수하지만, 초기값의 부정확, 모델 오차, 외란 등의 예상하지 못하는 상황에서 급격한 성능저하가 발생할 수 있다. 본 논문에서는 새로운 디지털 위상 고정 루프를 설계 하기 위해 최적의 측정값 구간 길이를 갖는 최소 공분산 유한 임펄스 응답 필터를 제안한다. 제안된 유한 임펄스 응답 필터의 중요 파라미터인 측정값 구간 길이를 구하기 위해 수치적 방법을 소개하며, 필터의 이득을 얻기 위해 비용함수로 오차의 공분산 행렬을 설정하고, 이를 최소화 하기 위하여 선형 행렬 부등식을 사용하였다. 제안된 디지털 위상 동기 루프의 우수성과 강인성을 검증하기 위해 노이즈 정보가 부정확한 상황에서 기존 방법과의 비교 및 분석을 위한 시뮬레이션을 수행하였다.

Keywords

Acknowledgement

이 논문은 2020년도 조선대학교 연구비의 지원을 받아 연구되었음.

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