Journal of information and communication convergence engineering

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Simulation-Based Fault Analysis for Resilient System-On-Chip Design

  • Han, Chang Yeop (Department of Electronic Engineering, Seoul National University of Science and Technology) ;
  • Jeong, Yeong Seob (Department of Electronic Engineering, Seoul National University of Science and Technology) ;
  • Lee, Seung Eun (Department of Electronic Engineering, Seoul National University of Science and Technology)
  • Received : 2021.07.23
  • Accepted : 2021.08.09
  • Published : 2021.09.30
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Abstract

Enhancing the reliability of the system is important for recent system-on-chip (SoC) designs. This importance has led to studies on fault diagnosis and tolerance. Fault-injection (FI) techniques are widely used to measure the fault-tolerance capabilities of resilient systems. FI techniques suffer from limitations in relation to environmental conditions and system features. Moreover, a hardware-based FI can cause permanent damage to the target system, because the actual circuit cannot be restored. Accordingly, we propose a simulation-based FI framework based on the Verilog Procedural Interface for measuring the failure rates of SoCs caused by soft errors. We execute five benchmark programs using an ARM Cortex M0 processor and inject soft errors using the proposed framework. The experiment has a 95% confidence level with a ±2.53% error, and confirms the reliability and feasibility of using proposed framework for fault analysis in SoCs.

Keywords

Acknowledgement

This study was supported by the Research Program funded by the SeoulTech(Seoul National University of Science and Technology).

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