The Journal of the Korea institute of electronic communication sciences (한국전자통신학회논문지)

Korea Institute of Electronic Communication Science (한국전자통신학회)
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Approximate Multiplier With Efficient 4-2 Compressor and Compensation Characteristic

효율적인 4-2 Compressor와 보상 특성을 갖는 근사 곱셈기

  • 김석 (건양대학교 의공학부) ;
  • 서호성 (전남대학교 전기전자통신컴퓨터공학부) ;
  • 김수 (전남대학교 전기전자통신컴퓨터공학부) ;
  • 김대익 (전남대학교 전기전자통신컴퓨터공학부)
  • Received : 2021.11.29
  • Accepted : 2022.02.17
  • Published : 2022.02.28
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Abstract

Approximate Computing is a promising method for designing hardware-efficient computing systems. Approximate multiplication is one of key operations used in approximate computing methods for high performance and low power computing. An approximate 4-2 compressor can implement hardware-efficient circuits for approximate multiplication. In this paper, we propose an approximate multiplier with low area and low power characteristics. The proposed approximate multiplier architecture is segmented into three portions; an exact region, an approximate region, and a constant correction region. Partial product reduction in the approximation region are simplified using a new 4:2 approximate compressor, and the error due to approximation is compensated using a simple error correction scheme. Constant correction region uses a constant calculated with probabilistic analysis for reducing error. Experimental results of 8×8 multiplier show that the proposed design requires less area, and consumes less power than conventional 4-2 compressor-based approximate multiplier.

근사 컴퓨팅은 효율적인 하드웨어 컴퓨팅 시스템을 설계하기 위한 유망한 방법이다. 근사 곱셈은 고성능, 저전력 컴퓨팅을 위한 근사 계산 방식에 사용되는 핵심적인 연산이다. 근사 4-2 compressor는 근사 곱셈을 위한 효율적인 하드웨어 회로를 구현할 수 있다. 본 논문에서는 저면적, 저전력 특성을 갖는 근사 곱셈기를 제안하였다. 근사 곱셈기 구조는 정확한 영역, 근사 영역, 상수 수정 영역의 세 영역으로 나누어진다. 새로운 4:2 근사 compressor를 사용하여 근사 영역의 부분 곱 축소를 단순화하고, 간단한 오류 수정 방식을 사용하여 근사로 인한 오류를 보상한다. 상수 수정 영역은 오차를 줄이기 위해 확률 분석을 통한 상수를 사용하였다. 8×8 곱셈기에 대한 실험 결과, 제안한 근사 곱셈기는 기존의 4-2 compressor 기반의 근사 곱셈기보다 적은 면적을 요구하면서 적은 전력을 소비함을 보였다.

Keywords

References

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