Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
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Multi-Level FeRAM Utilizing Stacked Ferroelectric Structure

강유전성 물질을 이용한 Multi-level FeRAM 구조 및 동작 분석

  • Seok Heon Kong (Seoul National University of Science and Technology) ;
  • June Hyeong Kim (Seoul National University of Science and Technology) ;
  • Seul Ki Hong (Seoul National University of Science and Technology)
  • Received : 2023.09.11
  • Accepted : 2023.09.30
  • Published : 2023.09.30
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Abstract

In this study, we developed a Multi-level FeRAM (Ferroelectrics random access memory) device utilizing different ferroelectric materials and analyzed its operation through C-V analysis using simulations. To achieve Multi-level operation, we proposed an MFM (Multi-Ferroelectric Material) structure by depositing two different ferroelectric materials with distinct properties horizontally on the same bottom electrode and subsequently adding a gate electrode on top. By analyzing C-V peaks based on the polarization phenomenon occurring under different voltage conditions for the two materials, we confirmed the feasibility of achieving Multi-level operation, where either one or both of the materials can be polarized. Furthermore, we validated the process for implementing the proposed structure using semiconductor fabrication through process simulations. These results signify the significance of the new structure as it allows storing multiple states in a single memory cell, thereby greatly enhancing memory integration.

본 연구에서는 서로 다른 강유전성 물질을 활용하여 Multi-level FeRAM (Ferroelectrics random access memory) 소자에 대한 구조를 제시하였으며, 이를 검증하기 위해 Simulation을 통한 C-V 분석을 수행하였습니다. Multi-level 소자를 구현하기 위해 두 가지 서로 다른 물성을 가진 강유전체를 동일한 하부 전극 위에 나란히 증착하고, 이후 게이트 전극을 위에 올린 MFM (Multi-Ferroelectric Material) 구조를 제안하였습니다. 두 강유전체가 서로 다른 전압 조건에서 분극 현상 (Polarization)을 나타내는 것을 바탕으로, 두 개의 물질 중 한 개만 polarization 되었을 때와 두 개 모두 polarization 되었을 때의 상황을 C-V peak 분석을 통해 확인하여 Multi-level 동작을 구현할 수 있음을 확인하였습니다. 더불어, 제시한 구조를 반도체 제조 공정을 활용하여 구현하는 방법을 공정 simulation을 통해 검증하였습니다. 이러한 결과는 하나의 메모리 셀에서 여러 상태 값을 저장할 수 있음을 의미하며, 이는 메모리의 집적도를 크게 향상시킬 수 있는 새로운 구조체로서의 가능성을 의미합니다.

Keywords

Acknowledgement

This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MSIT) (No. RS-2023-00239657).

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