In this paper, we present narrowband interference (NBI) cancelling algorithm applied to wideband spread spectrum system. We introduce multi-carrier transmission technique to overcome hardware inplementation difficulty of wideband spreading above 40MHz and to enhance NBI performance. A direct-sequence spread spectrum receiver using both decision-feedback and two sided LMS filters for combating narrowband interference is applied. We show that performance of this receiver outperforms conventional NBI rejection systems in tone jamming, partial band jamming, and impulsive channel through the bit error ratio evaluation. In addition, we propose a new technique to improve the performance of time domain NBI rejection algorithm sensitive to impulsive channel.

전력선은 백색 가우시안 배경 잡음뿐 아니라 임펄스 잡음, 고조파 잡음 등의 비 가우시안 잡음들로 인해 통신 채널로서 열악한 전송 특성을 나타낸다. 또한 좁은 가용 대역폭으로 인해, 광대역 특성이 요구되는 DS-CDMA 방식과 같은 대역 확산 시스템의 적용에 한계가 있다. 본 연구에서는 차세대 고속이동통신을 위한 다원접속/변조방식인 멀티코드 (multi-code) CDMA 방식과 이에 길쌈 부호와 인터리빙 등의 부호화 기능을 더한 시스템을 전력선 통신 시스템에 적용하고, 모의실험을 통해 전력선 채널의 비 가우시안 잡음의 영향을 매우 효과적으로 보상할 수 있음을 확인하였다.

Many of the currently used PN code acquisition algorithms detect the phase of the incoming PN signal on the basis of ML estimation principle and utilize statistics grounded in taking inner products. As an extension of PN code acquisition algorithm using one auxiliary code introduced by Salih in 1996, we propose a more and optimal (hardware / time / space complexity wise) algorithm by using a vector space approach. We outline some important differences between our algorithm and that introduced by Salih and in the process point out some advantages of our algorithm.

In this Paper, we discuss reducing the number of orthogonal code in Multi-Code CDMA (MC-CDMA) system. MC-CDMA system is highlighted for multi-media communication services, but conventional MC-CDMA(CMC-CDMA) system are needed many more orthogonal codes compared to traditional direct sequence CDMA(DS-CDMA) systems. in this paper, we propose the system which can reduce the number of orthogonal codes using sub-orthogonal code(SOC) technique. We certificate that the performance of the proposed system shows the almost same result under gaussian noise environment as compared to CMC-CDMA system through Monte-Curio computer simulation method.

본 논문에서는 증가하는 광대역 무선 서비스의 수요에 부응하기 위해서 이미 제정되었거나 현재 제정중인 무선 LAN 표준안으로서 IEEE 802.11, ETSI BRAN의 HIPERLAN, WIN Forum의 SUPERNET, MMAC-PC, ATM Forum의 WATM-WG 규격의 동향에 대하여 살펴본다. 또한 ETSI BRAN과 MMAC-PC 등에서 무선 LAN의 공통된 물리계층 표준안으로 현재 추진 중이고, 5㎓ 대역의 무선 ATM 모뎀 표준안과도 직접적인 관련이 있는 OFDM 방식의 IEEE 802.11a 무선 LAN 모뎀 기술에 대하여 기술한다.

A spatio-temporal vector channel model is introduced for the position location (PL) estimation problem for CDMA cellular system environment. Two common ways for the PL make use of the AOA (Angle Of Arrival) and TDOA (Time Difference Of Arrival) from a subscriber to the multiple sensors (base stations). In this paper, we applied the derived vector channel to simulate the multipath channel for the angle of the signal arrival in CDMA systems. Cross-correlation method is a good candidate among other direction finding algorithms available in literature, especially in wideband modulation as in the CDMA system. The PL estimation errors are evaluated for different channels, which are obtained as a parameter of scattering radius of the suggested model. We noted that the number of sensors (base-stations) are related to the PL errors in favor of the available data.

In this paper, the improved initial cell searching algorithm is proposed for 3GPP W-CDMA system. The key objective of the proposed algorithm is to utilize the reliability of the first stage of cell searching algorithm in order to accomplish the second stage. So the proposed algorithm makes the mobile station transfers to the second stage from the first stage, just after the slot synchronization is declared successively at the same time-offset. In order to compare the proposed algorithm with the conventional one, the simulations are accomplished for cell search algorithm for 3GPP W-CDMA systems in the multipath Rayleigh fading channel. Some parameters are also presented for the better performance in the initial cell searching algorithm.

In this paper, we propose bandwidth management scheme to efficiently guarantee the QoS of various services on ATM based IMT-2000 networks. The proposed bandwidth management scheme consists of the call admission control to reduce a handoff failure probability and the scheduling scheme to efficiently allocate a time slot based on the QoS requirements in wireless links. The simulation results show that the proposed bandwidth scheme has better performance than the previous works in terms of the handoff failure probability and packet delay time.

In this paper, a method based on the turbo principle is presented which combines diversity reception, equalization, and channel decoding, to combat the high transmission losses over the frequency-selective fading channel. The simulation results show that with the method presented, the BER performance within 0.3 ㏈ from that on the AWGN channel can be obtained over the frequency-selective fading channel in the investigated scenarios.

Blind equalizers recover the transmitted data using signal's statistical characteristics only. Because of its computational simplicity and fast convergence rate, CMA is widely used in practice. Blind equalizers, however, converge much slowly than conventional equalizers which use the training signals. In order to improve the convergence rate, many modified blind equalization algorithms have been proposed. Among those, Normalized CMA (NCMA) was applied to increase the convergence rate by using the large step size. Unfortunately it can only be applied for the constant modulus signal constellation scheme. this paper, we propose the Selective NCMA (SNCMA) that improve the convergence rate of blind equalization algorithms by using NCMA for non-constant modulus signalling method such as QAM constellation. We achieved fast start-up convergence rate and reduced steady-state residual error.

Adaptive channel equalization accomplished without resorting to a training sequence is known as blind equalization. The Constant Modulus Algorithm(CMA) and Modified CMA(MCMA) are widely referenced algorithms for blind equalization of a QAM system. This paper proposes a hybrid scheme of CMA and MCMA with Carrier Recovery that is robust for high level QAM with low steady state tracking error.

It is well known that the OFDM transmission is weak against the frequency offset. We evaluate the BER performance of the OFDM system with guard interval and simple one-tap equalizer bank. For the small frequency offset, the loss in $E_{b}$ $N_{o}$ is about 1㏈ at required BER = 10$^{-5}$ , when the mean value of the second-ray's attenuation coefficient is 0.25 and the normalized frequency offset, which is normalized about OFDM symbol time, is 5%.%.%.

For the asymmetric digital subscriber line communications, the paper proposes a new echo canceller with the so-called CALAOI(CAscade of LAttice and Orthogonalized IIR) structure, which comprises of a lattice and an orthogonalized IIR structure. Through simulations, the CALAOI echo canceller was verified to have much fewer complexity of computations and has faster convergence speed than conventional FIR echo canceller. The CALAOI echo canceller is predicted to maximize performances of communication services in high speed communications such as VDSL, GIGA bit Ethernet, and so on as well as ADSL.

CDMA receiving algorithms, such as single/multi user detector and smart antenna system which have been proposed to suppress ISI and MAI. still suffer from the residual interferences among the output signals. A blind adaptive CMA post-processing technique, which is able to suppress the residual ISI and MAI symbol-by-symbol was proposed. It can be easily applied to any conventional detector at the expense of a small amount of additional computations. In this paper, a solution for the convergence problem of proposed method is proposed and analyzed. Through computer simulations it was shown that the proposed method has stable convergence property and good performance in BER.

Echo and near-end crosstalk(NEXT) can be generated in two-wire duplex transmission. In this paper investigates how to cancel echoes of high speed communication. A pipeline algorithm is used to remove the echoes that high speed communication. It is least mean squared(LMS) algorithm based on the relaxed look-ahead concept, is focused on the pipelined LMS, and its performance is compared to that of the serial LMS algorithm. And we design pipelined adaptive filtering. In advanced of the hardware implementation with VHDL code the performance of pipelined LMS algorithm is verified by the computer simulation.

DS-CDMA is used to widely spread spectrum for a cellular mobile digital communication that maximizing users- capacity at the limited frequency bandwidth, solving technical matters with the channel. Especially, the capability of a spread spectrum receiver relied on fast code acquisition time at the demodulation. In this paper, we considered that fast code acquisition time when a spread spectrum system is designed, and existed code acquisition system set up one code epoch on a position at initial processing, but the proposed code acquisition system improved that two code epoch are set up at the same time, therefore code acquisition time is diminished in effect. The structure modeling to VHDL language. Its synthesized the synthesized and, is implemented FPGA chip

본 논문에서는 이동 무선 채널에 의한 동영상의 실시간 전송을 위해 채널 상태에 따라 터보코드의 반복 복호 횟수를 자동으로 결정한 UEP(Unequal Error Protection) 채널 부호화 방법에 대해 레일리 페이딩 채널에서의 성능을 분석한다. 이 부호화 방법은 열악한 채널 환경에서 우선 순위가 높은 정보에 보다 많은 반복 횟수가 부과되게 함으로써 헤더 정보나 움직임 벡터 등과 같이 동영상 신호의 복원에 중요한 정보에 대한 오류의 전파효과를 억제시킬 수 있다. 연집 오류의 주요인인 레일리 페이딩 채널에서 복호기의 성능을 분석하기 위해 컴퓨터 모의실험을 수행해 그 결과를 제시한다.

The iterative usage of soft outputs increases the performance of digital radio receiver. The feedback of reliability information reduces the channel estimation errors and increases the performance of equalization. This paper investigates the turbo equalization techniques for wireless cellular systems over continuous time varying channel. Simulation results over a GSM channel were presented.

In this paper, it was studied that the performance of OFDM transmission scheme was improved in fading channel by applying TCM, which has advantages of error correction and bandwidth efficiency. Simulation was carried out for two TCM models with different code efficient length. By mapping two models to square 16QAM, the model with the code efficient length of 2 achieved 3㏈ better than the other for the BER of 10$^{-3}$ . In conclusion, if we want to achieve a better performance with TCM in OFDM applications, we should select a TCM with langer code efficient length.

In this paper, a serially concatenated space-time code (SCSTC) with bandwidth efficiency and high data rate is studied. The suggested SCSTC is composed of space-time code, the convolutional code and Interleaver. The SCSTC has a very high BER performance than the conventional space-time code. The BER performance of the suggested SCSTC can be proven by using computer simulation through the iterative decoding method. The first decoder uses Symbol-MAP algorithm and the second decoder uses Bit-MAP algorithm for decoding tile information bits. The simulation results show the performance of the suggested SCSTC is better than the conventional Space-Time Code.

This paper describes on the threats such as IP spoofing, denial of service, and ILMI based attack etc. for IP over ATM network. Especially we discuss on the threats due to ATM characteristics that are VC stealing, multiparty and multi-connection call. Also we investigate on the threats of ATM based MPLS network. Finally we discuss and suggest the various solutions of ATM security.

ATM을 근간으로한 초고속 정보 통신망은 융통성 및 효율성, 고속의 정보 전송 능력으로 인해 미래의 통신망으로 자리잡을 것으로 예상되며, 이와 같은 초고속 정보 통신망은 완전히 구축되기 전까지는 프레임릴레이 등과 같은 기존의 망들과 혼용해서 사용될 것이기 때문에 망 발전의 중간 단계에서 경제성이나 기술의 효용성 문제로 기본망과의 연동 연구는 매우 중요하다고 할 수 있다. 이에 따라 본 논문에서는 교환 가상 채널(Switched Virtual Channel SVC) 기반의 제어평면 연동을 고려하여 프레임 릴레이와 ATM간의 신호 연동을 중심으로 망간 연동 프로토콜을 설계하고 검증하였다.

Mobile network applications are growing and this requires a fast and efficient transport method between the BS(Base Station) and the MSC(Mobile Switching Center). One possible solution is to use ATM and a voice CODEC standard which compresses 64kbps voice data to less than 8kbps. The low bit tate and small-sized packets made by the voice CODEC imply that significant amount of link bandwidth would be wasted, if this small-sized packet is carried by one ATM cell. The cell assembly delay increases if one ATM cell is fully filled with the small-sized packets. For the bandwidth-efficient transmission of low-rate, short, and variable length packets in delay sensitive applications, AAL-2 was standardized. This paper evaluates performance of AAL-2 by using voice CODEC standard.

본 논문은 서비스 제어 시스템(Service Control Point : SCP), 서비스 교환 시스템(Service Switching System : SSP), 그리고 지능형 정보제공 시스템(Intelligent Peripheral : IP)을 물리적 구성 요소로 하는 차세대지능망 (Advanced Intelligent Network : AIN) 서비스중 주요 서비스인 자동콜렉트콜(Automatic Collect Call : ACC) 서비스에 대한 지능형 정보제공 시스템에서의 자원 제공시간 (점유 시간)을 분석한 것이다. 차세대 지능망 구성요소들이 연동되어 서비스되는 상황에서 지능형정보 제공시스템에서의 서비스 시나리오를 제시하였으며, 특수 자원에 대한 자원 제공 점유 시간을 분석하였다.

In this paper, we define the high-speed router as a router, which can support aggregated ports over 25Gbps, and provide issues and trends in high-speed router design. We propose design considerations on IP packet forwarding, switching fabric, packet scheduling and buffer management, network resource reservation, and router operation and administration.

In this paper, we propose more effective method of label allocation on Multi-Protocol Label Switching (MPLS) which is IP over ATM integrated model. We research the problems, one is using downstream label allocation method case, the other is using both downstream and upstream label allocation method. Easily we can solve this problem through the downstream-on-demand label allocation method with RSVP(Resource ReSerVation Protocol). In experiment we can find 1.5~28% error which will be fixed by using downstream-on-demand label allocation method.

This paper presents a hardware architecture of AAL(ATM Adaptation Layer) type 2 switch. The proposed architecture can assign and configure maximum AAL2 CID limit. AAL2 is the protocol which has been recommended by ITU-T and ATM-Forum for low bit rate delay sensitive services. The architecture assumes 155 Mbps STM-1/STS-3c physical interface, maximum VCC can be 64K connections. It can support maximum 16,384M AAL2 connections. For efficient use of peripheral memory, a concept of segment address was proposed. The proposed AAL2 switch hardware architecture can be used in ATM network as a standalone server or embedded module in a ATM switching system.

Input queueing is useful for high bandwidth switches and routers because of lower complexity and fewer circuits than output queueing. The input queueing switch, however, suffers HOL-Blocking, which limits the throughput to 58%. To get around this low throughput, we propose a simple scheduling algorithm called Synchronous Input Port (SIP). This method synchronize packets and switching without blocking, which is shown to have better performance over the established algorithms

In a packet-switched wireless cellular network, a packet destined to a mobile station is queued at a base station and then broadcast over the base station's cell. When an active mobile station leaves a cell, there re-main packets which are destined to the mobile and not yet delivered to it at the cell's base station. For application which are sensitive to packet losses, such back- logged packets must be forwarded to the new base station. Otherwise, an end-to-end retransmission may be required. However, an increase in packet delay is incurred by employing the packet forward scheme, since a packet may be forwarded many times before it is delivered to the destined mobile station. For an enhanced quality-of-service level, it is preferred to reduce tile packet delay time. In this paper, we develop an analytical approximation method for deriving mean packet delay times. Using the approximation and simulation methods, we investigate the effect of network parameters on the packet delay time.

In this paper, we propose a QoS-sensitive admission threshold method for the transmission of the non-real tine data packet such that the quality of services for both voice and data traffics are maintained to a required level. By detecting the active voice traffic during the current time slot, the non-real-time data packets are transmitted up to an admission threshold level during the next time slot. We found out that the optimum admission threshold is four voice traffic resources lower from the maximum allowable threshold to maintain the outage probability within 1% when the connected voice users are 15.

In this Paper, new congention control schemes using the adaptive rate control for ATM LANs are presented. If is preferable for hosts in LANs to be able to send bursts at the same speed as the interface link speed in a lightly loaded condition, and as the network load increases, to reduce their traffic rate adaptively in order to avaid network congestion. We propose to apply such a rate control concept for two different traffic classed in the ATM LANs. For the first traffic class requiring no bandwidth reservation, i.e, a best effort service class, a combination of the end-to-end adaptive peak rate control with the link-by-link backpressure control is proposed. For the second traffic class, requiring the bandwidth reservation for the burst transmission, i.e. guaranteed burst service class, a combination of he adaptive peak rate control with the fast bandwidth reservation is proposed.

In this paper, we designed each matching networks by given input and output impedances of power amplifiers. Mearsured results for IMD and gain flatness are -30㏈c and $\pm$0.2㏈ with 38㏈m output power PEP of PTE10119 at 2.10-2.20㎓ and are -30㏈c and $\pm$0.4㏈ with 42㏈m output power PEP of MRF284 at same frequency range.

In this paper, a method of Radome design is considered. The shape is similar to tangent-ogive, and the antenna is a waveguide broad-wall slot array antenna. The characteristic of the Radome material is obtained by measuring test samples. By analyzing the transmission efficiency of the flat plate, Radome wall thickness is determined firstly. And then, the detailed characteristics of the Radome are analyzed by using GO-PO approximation technique. Several simple parameters of the designed Radome are tested and compared with the simulation results.

The traditional FDTD method in the stair case, the CP-FDTD method, the modified CP-FDTD method, and Dey method have been developed to analyze smooth-curved- surface structures. These methods have some disadvantages such as inaccuracy of the stair-case FDTD, instability of the modified CP-FDTD, and complexity of Dey method. The improved algorithm presented here is a mixed-form of the modified CP algorithm and Dey algorithm. It is to avoid collinear borrowing approximations and to manipulate field update equations. All of preceding methods are applied to the E-plane sectoral horn antenna to get far-field patterns. The validity and applicability of the presented one is to be shown by comparing computed far-field patterns with measured values.

A T-shaped microstripline-fed printed slot array antenna having wide bandwidth, high gain, and narrow bandwidth is presented in this paper. The proposed antenna is analyzed by using the transmission line model method. We fabricated 4$\times$1 microstrip slot array antenna and measured its return loss and radiation pattern. The maximum bandwidth of this array antenna is from 1.43 ㎓ to 2.60 ㎓, which is 58.1% for the VSWR $\leq$ 2.

In this paper, we showed parasitic effects in the millimeter wave package, and proposed a suppression method of parasitic effects using Si lossy layer. From CB-CPW used as a transmission line of the MIMIC package, PPL mode is generated and this causes the parasitic effects considered from this paper. Parasitic effects caused by PPL mode such as resonance, radiation, and crosstalk in the single and multi-chip package ran affect to the performance of MIMIC seriously. To suppress these parasitic effects, we adapted Si lossy layer $\rho$ . The PPL mode can be suppressed by the lossy layer, and it eliminates the parasitic effects. It is expected that showed results ran be used as luxurious data for design MIMICs and various types of millimeter wave applications.

This paper describe the design and measurements of dual PLL for IMT-2000 cellular phone. As a result, dual PLL was well-operated in the RF frequency ranges of 2300 ~ 2360 MHz and If frequency of 380 MHz. The output power of -4.28 ㏈m, phase noise of -107.66㏈c/Hz at 100KHz frequency offset, lock time of 675.6$mutextrm{s}$ were obtained at 2330MHz. The output power of -4.78 ㏈m, phase noise of -115.28㏈c/Hz were also obtained at 380MHz.

In this paper, we have designed and fabricated a MMIC power amplifier for X-band using AlGaAs/InGaAs/GaAs PM-HEMTs and passive devices such as Ti thin film resistors, rectangular spiral inductors and MIM capacitors. The fabricated MMIC power amplifier for X-band shows that S/ sub 21/ and S$_{11}$ are 14.804 ㏈ and -29.577 at 8.18 GHz, respectively. The chip size is 1.86$\times$1.29 $\textrm{mm}^2$.>.>.

In this paper, frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop). For improving phase noise characteristic Voltage Controlled Oscillator was fabricated using coaxial resonator and eliminated frequency divider using SPD as phase detector and increased open loop gain. Fabricated frequency synthesizer had 1.82㎓ center frequency, 160MHz tuning range and -119.73㏈c/Hz low phase noise characteristic.

본 논문에서는 마이크로스트립 안테나에 대한 최근의 국내외 주요 연구 결과를 요약 정리하고, 몇 가지 설계 예를 제시하였다. 단일 방사 소자 기순 동향은 광대역 안테나, 이중공진 안테나, 이중편파 안테나, 원형편파안테나로 구분하여 최초의 개발 동향을 중심으로 기술하였다. 배열화에 있어서는 기존의 연구결과를 정리하고 몇 가지 설계 예를 제시하였다.

Frequency responses of the surface acoustic wave(SAW) filters are simulated by using the impulse modeling. The simulation technique of the SAW filters is to use the Fourier transformation to make a correspondence between the impulse response of the filter and the taps in the delay line. Since the Fourier series must be truncated after a finite number of terms, window functions are often used to weight the coefficients to obtain the desirable side-lobe level and bandwidth. The filter design is operated through the iterative simulation procedures. The design process is capable of yielding filters with optimized frequency response characteristics.

A two-stage monolithic microwave integrated circuits (MMIC) broad-band power amplifier with AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) has been developed for the up-link and down-link applications for local multipoint distribution systems (LMDS) in the frequency range of 24~28㎓. The amplifier has a small signal gain of 18.6㏈ at 24.5㎓ and 16.7㏈ at 27.1㎓. It achieved output powers of 19.8㏈m with PAE of 19.8% at 24.5㎓ and 18.8㏈m at 27.1㎓.

This paper presents the accurate deembeding method for pad and parasitics of MOSFET device. rad effects are deembedded using THRU LINE, which is much simpler method without laborious fitting procedure compared with conventional OPEN and SHORT pad modeling. Parasitic resistance extraction uses the algebraic relation between increments of inversion layer charge and oxide capacitance. It is especially adequate for insulating gate junction device. Extracted parasitics are verified through comparing modeled and measured S parameters.

We have developed fabrication processes that form a wide-head T-gate with a 0.2 ${\mu}{\textrm}{m}$ gate length using the combination of thickness of each PMMA layer, line doses and development times for applications in millimeter- and micro-waves monolithic integrated circuits. The three-layer resist structure (PMMA/P(MMA-MAA)/PMMA = 1800 $\AA$/5800 A/1900$\AA$), 4nC/cm and over development were used for fabrication of a wide-head T-gate by the conventional double E-beam exposure technology. The experimented results show that the cross sectional area of T-gate fabricated by the proposed method is easily enlarged without additional processes.

Switching behaviour of the ferroelectric thin film and device characteristics of the MFSFET (Metal-Ferroelectric-Semiconductor FET) are simulated with taking into account the accumulation of oxygen vacancies near interface between the ferroelectric thin film and the bottom electrode caused by the progress of fatigue. We show net switching current decreases due fatigue in the switching model. It indicates that oxygen vacancy strongly suppresses polarization reversal. The difference of saturation drain current of the device before fatigue is shown by the dual threshold voltages in I$_{D}$-V$_{D}$ curve as 6㎃/$\textrm{cm}^2$ and decreases as much as 50% after fatigue. Our simulation model is expected to play an important role in estimation of the behavior of MFSFET device with various ferroelectric thin films.lms.

A Bi$_4$Ti$_3$O$_{12}$ (BIT) thin film is prepared by sol-gel method using acetate precursors and evaluated whether it could be applied to NVFRAM. The drying and the annealing temperature are 40$0^{\circ}C$ and $650^{\circ}C$, respectively and they are determined from the DT-TG analysis. The BIT thin film deposited on Pt/Ta/SiO$_2$/Si substrate shows orthorhombic perovskite phase. The grain size and the surface roughness are about 100 nm and 70.2$\AA$, respectively. The dielectric constant and the loss tangent at 10 KHz are 176 and 0.038, respectively, and the leakage current density at 100㎸/cm is 4.71$mutextrm{A}$/$\textrm{cm}^2$. In the results of hysteresis loops measured at $\pm$250㎸/cm, the remanent polarization (Pr) and the coercive field (Ec) are 5.92$mutextrm{A}$/$\textrm{cm}^2$ and 86.3㎸/cm, respectively. After applying 10$^{9}$ square pulses of $\pm$5V, the remanent polarization of the BIT thin film decreases as much as about 33% from 5.92 $\mu$C/$\textrm{cm}^2$ of initial state to 3.95 $\mu$C/$\textrm{cm}^2$.

반강유전 물질인 Pb[(Zr. Sn)Ti]NbO₃를 La/sub 0.5/Sr/sub 0.5/CoO₃/Pt/Ti/SiO₂/Si 기판상에 RF 마그네트론 스퍼터링 방법으로 박막화하여 그 결정성과 전기적 특성을 조사하였다. 80 W의 RF power, 400℃의 기판온도, Ar:O₂= 9:0.5의 분위기에서 증착되고, 650 ℃에서 10초동안 RTP(Rapid Thermal Process) 방법으로 열처리된 박막이 가장 우수한 페로브스카이트 구조를 보였으며, 10 ㎑ 에서 유전상수(ε')는 721, 유전손실(tan δ)은 0.06을 나타내었다. 잔류분극(Pr)은 15.5 μC/㎠ 였으며, 항전계(Ec)는 51 ㎸/㎝로 비교적 낮은 값을 나타내었다.

In this paper we report new integration technology developed for three-dimensional metallic microstructures in an arbitrary shape. We have developed the two fabrication methods: Multi-Exposure and Single-Development (MESD) and Sacrificial Metallic Mold(SMM) techniques. Three-dimensional photoresist mold can be formed by the MESD method while unlimited number of structural levels can be realized by the SMM technique. Using these two techniques we have fabricated solenoid inductors and levitated spiral inductors for RF applications. We have achieved peak Q- factors over 40 in the 2-10㎓ range, the highest number among the inductors reported to date. Finally, we propose "On-Chip Passives" as a post IC process for monolithic integration of inductors, tunable capacitors, microwave switches, transmission lines, and mixers and filters toward future single-chip transceiver integration.

Abstract - Electrical characteristics or asymmetric n-MOSFET's with different source and drain geometry are experimently investigated using test structures having various gate width. Saturation drain current and resistance in linear region are estimated by a simple schematic model, which consists of conventional device having parasitic resistor. A comparison of experimental results of symmetric and asymmetric devices gives the parasitic resistance caused by abnormal device structure. The suggested model shows good agreement with the measured drain current for both forward- and reverse-modes.

High-speed device is essential to optoelectric IC for optical storage system such as CD-ROM, DVD, and to ADC for high-speed communication system. This paper represents the BiCMOS process which contains high-speed SAVEN bipolar transistor and analyzes the frequency and switching characteristics of it briefly. Finally, to prove that the SAVEN device is adequate for high-speed system, latched comparator operating at 500MHz is designed with the SPICE parameter extracted from BiCMOS device simulation.

A simple two-terminal cyclic current-voltage(I-V) technique is used to measure the current-transients in MOS capacitors. Distinct charging/discharging currents were measured and analyzed as a function of (1) the hold time. (2) the gate polarity during the FNT electron injection, (3) the injection fluence and (4) the annealing time after the injection had stopped. Discharging and charging current-transients were strongly dependent upon the conditions for forming the inversion layer and the density of interface traps caused during the FNT electron injection, respectively. Several tentative mechanisms were suggested in the current work.

Conventional double DES has been not only shown to have a vulnerable drawback to attack method called 'Meet-in-the-Middle', but also to be hard to use that it is because software implementation has a number of problem in real time processing. This paper describes the design and implementation of modified Isolated double DES algorithm using VHDL for resolving the above problems. In this approach, we also discuss an efficient method for increasing cipher strength through expansion of key length.

This paper presents a design of the real-time preprocessor for CMOS image sensor suitable to the digital camera applications. CMOS image sensor offers some advantages in on-chip integration, system power reduction, and low cost. However, it has a lower-quality image than CCDs. We describe an image enhancement algorithm, which includes color interpolation, color correction, gamma correction, sharpening, and automatic exposure control, to compensate for this disadvantage, and present its efficient hardware architecture to implement on the real-time processor. The presented real-time preprocessor was designed using VHDL, and it contains about 19.2K logic gates. We also implement our system on FPGA chips in order to provide the real-time adjustment and it was successfully tested.

This paper describes the design and implementation of an application specific instruction-set processor developed for embedded DSP applications. The instruction-set has an uniform size of 16 bits, and supports 3 types of instructions: Primitive, Complex, and Specific. To reduce code size and cycle count we introduce complex instructions that can be selected according to the application under consideration, which leads to 50% code size reduction maximally. The processor has two independent data memories to double the data throughput and the address space. The processor is synthesized by 0.6$\mu$m single-poly double-metal technology. Critical path simulation shows that the maximum frequency is 110MHz and total gate count is 132, 000.

In this paper, we present a coprocessor that can operate with ARM microprocessors. The coprocessor supports IEEE 754 standard single- and double-precision binary floating point arithmetic operations. The design objective is to achieve minimum-area, low-power and acceleration of processing power of ARM microprocessors. The instruction set is compatible with ARM7500FE. The coprocessor is written in verilog HDL and synthesized by the SYNOPSYS Design Compiler. The gate count is 38,115 and critical path delay is 9.52ns.

This paper describes a low-power design of decimation filter. To reduce power consumption, an approximate processing method which controls the error in canonic signed digit(CSD) coefficients is proposed. The CSD representation reduces the number of operations by representing multiplications with add and shift operations. The proposed method further reduces the number of operations by controlling the error of CSD coefficient. Processor type architecture is used to implement the proposed method. Simulation result shows that the number of operations is reduced to 56%, 35% and 10% at each approximated filter level.

This paper presents a data-dependent precharge suppression(DPS) D-flip-flop(DFF) with precharge suppression scheme according to data-transition probability The main feature of the DPS DFF is that precharge is suppressed when there is no data transition. The proposed DPS DFF consumes less power than the conventional Yuan-Svensson's true single phase clocking(TSPC) DFF when the data-transition probability is low. The simulation result shows that the power consumption is reduced by 42.2 % when the data-transition probability is 30%.

In this paper, a low voltage CMOS analog four-quadrant multiplier is presented. The proposed multiplier is composed of a pair of transconductor and lowers supply voltage down to $V_{T}$+2 $V_{Ds,sat}$+ $V_{DS,triode}$. The designed analog four-quadrant multiplier have simulated by HSPICE using 0.25${\mu}{\textrm}{m}$ n-well CMOS process with a 1.2V supply voltage. Simulation results show that the THD can be 1.28% at maximum differential input of 0.7 $V_{p-p}$././.

이동 통신의 발달로 가속화된 고주파 반도체 소자 기술 중 새로운 가능성을 가진 mm-wave 대역의 주용 응용 분야를 살펴보았다. 향후 이 분야의 응용을 위한 소요 기술, 주요 소자 기술을 살펴보고 국내의 기술 동향을 알아보았다. 국내 연구 기관 중 LG 종합기술원에서 mm-wave 분야의 기술 개발 방향 및 최근의 개발 결과를 소개하였다.

In this paper V-I(Voltage to Current) converter using the series composite transistor is presented. Due to the series composite transistor employs operating in the saturation region and triode region, the proposed circuit has wide input range at low voltage. The designed V-I converter has simulated by HSPICE using 0.6${\mu}{\textrm}{m}$ n-well CMOS process with a $\pm$2.5V supply voltage. Simulation results show that the THD can be 0.81% at 4 $V_{p-p}$ differential input voltage when frequency of input signal is 10MHz.z.

This paper describes a 40-Msample/s 10-bit CMOS folding and interpolating analog-to-digital converter (ADC). A new 2-step architecture is proposed. The proposed architecture is composed of a coarse ADC bloch for the 6bits of MSBs and a fine ADC block for the remaining 4bits. The amplified folding analog signals in the coarse ADC are selectively chosen for the fine ADC. In the fine ADC, the bubble errors of the comparators are corrected by using the BGM(binary-gray-mixed) code[1] and extra two comparators are used to correct underflow and overflow errors. The proposed ADC was simulated using CMOS 0.25${\mu}{\textrm}{m}$ parameters and occupies 1.0mm$\times$1.0mm. The power consumption is 48㎽ at 40MS/s with 2.5-V power supply. The INL is under $\pm$2.0LSB and the DNL. is under $\pm$1.0LSB by Matlab simulations.

This paper presents the design of highly efficient one-chip CMOS DC/DC converter. The converter operates at the switching frequency of 1MHz for reducing the size of passive elements. And use the zero voltage switching(ZVS) for minimizing switching loss at high frequency. The simulation shows that the circuit can achieve a 95% efficiency while delivering a load of 1W at 2V output.

In this work, a A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10MS/s for video applications. This architecture is proposed using the Pipelined architecture for high speed conversion rate and the Successive - Approximation architecture for low power consumption, and consists of two identical stages that consist of sample/hold circuit, low power comparator, voltage reference circuit and MDAC of binary weighted capacitor array. Proposed A/D converter is designed using 0.25${\mu}{\textrm}{m}$ CMOS technology The SNR is 80㏈ at a sampling rate of 10MHz with 1.95MHz sine input signal. When an 8bit 10MS/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are $\pm$0.5 / $\pm$2 LSB, respectively. The power consumption is 13㎽ at 10MS/s.

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer (DDFS) is proposed. In the case that ROM is used for sinusoidal value calculation, reducing the size of ROM is significant. So the power consumption is affected mostly by its bit width. In the proposed method, the ROM bit width is reduced by 1 bit using the phase subtraction and the approximation. The spurious level is better than 80㏈c and the power consumption estimated is 510㎼/MHz.

This paper proposes a simple architecture of digital dividing block in dual-modulus prescaler phase-locked loop used in the wireless communication. Proposed architecture eliminates a swallow counter in the conventional one and demonstrates the advantages in reducing the power consumption and the gate-counts. Therefore, it is suitable for small die area and low power applications. The circuit is designed in a standard 0.35${\mu}{\textrm}{m}$ CMOS process.

In this paper, Dual PFD(Phase Frequency Detector) with improved phase locking time is proposed. The proposed PFD consists of positive and negative edge triggered D flip-flop. In order to confirm the characteristics of proposed PFD, HSPICE simulations are performed using a 0.25${\mu}{\textrm}{m}$ CMOS process. As a result of simulations, the proposed PFD has a characteristic of fast phase locking time with dead zone free.

Frequency divider selects the channel of the frequency synthesizer. General programmable divider has many flip-flops to realize all integer division value and stability problem by using dual modules prescaler. In this paper, a new architecture of programmable divider is proposed and designed to improve these problems. The proposed programmable divider has only thirteen flip-flops. The programmable divider is designed by 0.65${\mu}{\textrm}{m}$ CMOS technology and HSPICE. Operating frequency of the programmable divider is 200MHz with a 3V supply voltage.

A 2㎓, low noise, low power CMOS voltage-controlled oscillator (VCO) with an integrated LC resonator is presented. The design of VCO relies heavily on the on-chip spiral inductor. An optimized spiral inductor with Q-factor of nearly 8 is achieved and used for the VCO. The simulated result of phase noise is as low as -l14 ㏈c/Hz at an offset frequency of a 600KHz from a 2㎓ carrier frequency. The VCO is tuned with standard available junction capacitors, resulting in an about 400MHz tuning range (20%). Implemented in a five-metal 0.25${\mu}{\textrm}{m}$ standard CMOS process, the VCO consumes only 2㎽ from a single 2.5V supply. It occupies an active area of 620${\mu}{\textrm}{m}$$\times$720${\mu}{\textrm}{m}$.

In the transmitter of optical fiber transmission systems, a time-division multiplexer combines several parallel data streams into a single data stream with a high bit rate. In this paper, we design a 2:1 (2-channels) time-division multiplexer using SiGe HBT with emitter size of 2$\times$8${\mu}{\textrm}{m}$$^2$. The operation speed is 10Gbps, the rise and fall times of 20-80% are 34ps and 35ps, respectively and the dissipation of power is 0.86W.

This paper presents a GaAs MESMET self oscillating mixer for high efficiency L-band frequency conversion with small chip area consumption. Main circuit topology is consist of cascoded two FET with resonating part. The circuit is designed as unstably nonlinear for limited frequency band. FET with drain shorted to source is used for frequency tuning element. Linear conversion gain of -18.83 ㏈ is achieved with 9mA and 4V consumption. Input 1㏈ compression point is more than 11㏈m. The chip area is 1.4$\times$1.4 mm.

AlGaAs/InGaAs power P-HEMTS (Pseudo-morphic High Electron Mobility Transistors) with 1.0-${\mu}{\textrm}{m}$ gate length for PCS applications have been fabricated. We adopted single heterojunction P-HEMT structure with two Si-delta doped layer to obtain higher current density. It exhibits a maximum current density of 512㎃/mm, an extrinsic transconductance of 259mS/mm, and a gate to drain breakdown voltage of 12.0V, respectively. The device exhibits a power density of 657㎽/mm, a maximum power added efficiency of 42.1%, a linear power gain of 9.85㏈ respectively at a drain bias of 6.0V, gate bias of 0.6V and an operation frequency of 1.765㎓.

밀리미터파 대역의 아날로그 광전송을 위한 진행파형 (travel ing wave, TW) 전계흡수 광변조기 (electroabsorption modulator, EAM)와 광수신기의 설계에 대해 발표하고자 한다. TW EAM 및 TW 광수신기의 일반적인 형태인 ridge-type의 co-planar waveguide (CPW)구조에서의 마이크로파의 전송특성을 3차원 FDTD로 분석하여 광파와 전파의 속도 정합 등을 이루는 최적화 구조를 설계하였다. TW EAM의 경우 광세기 변조의 비선형 응답특성에 있어서 마이크로파 손실과 소자길이가 RF 신호의 혼변조 왜곡 (intermodulation distortion)과 SFDR (spurious free dynamic range)성능에 미치는 영향도 이론적으로 조사하였다. TW PIN 광수신기의 경우 광파와 마이크로파의 속도정합의 영향과 이전에는 고려되지 않았던 photo-generated 전송자의 진성 영역에서의 transit time이 광수신기의 밴드 폭에 미치는 영향을 분석하여 최적화 설계하였다.

An all fiber coupler-type add/drop filter has been fabricated by writing a Bragg grating in the coupling region of a fused fiber coupler. Some testing results will be discussed.

Fiber Bragg gratings have many applications such as fiber sensors, band-stop filters, add-drop filters, and mode convertors. In this paper, we present the fabrication method of various fiber Bragg gratings by using continuous wave UV-Argon(frequency-doubled Argon) laser. In our experiments, hydrogenation of fibers was used to enhance photosensitivity of fiber. And we fabricated fiber gratings by the phase mask method.

We present a 64-channel wavelength multiplexing architecture consisting of two 32-channel wavelength muitiplexers. Measured insertion losses of the 32-channel muitiplexers were below 8㏈ with uniformity in loss among channels better than 1㏈. The architecture of an OADM is also presented which employs FBGs. It is shown that the OADM can add or drop up to 12 channels.

We report fiber guiding experiments on the Photonic Quantum Ring(PQR) laser diode. In the 1km transmission measurements, we find that the PQR performs much better than the VCSEL. This suggests that the PQR laser is very promising candidate for LAN-range optical data communications. On the other hand, we have also fabricated 8$\times$8 PQR laser arrays and measured spatial decays for free space properties without using any guiding optics, which showed about 1m distance of spectral angle sensing.

In this paper, we demonstrate a polarization independent optical phase modulator using electro-optic polymer, P2ANS. To overcome the intrinsic polarization dependency of electro-optic effect, we control the optic axis using a new electrode structure. P2ANS(42:75) and P2ANS(25:75) are used for the core layer and the cladding layer, respectively. The buried-type single mode waveguide is fabricated by oxygen ion reactive etching and electic poling is performed by applying 1, 200V at 135$^{\circ}C$. The measured V$_{\pi}$ of the device for both TE and TM modes are 70V.

A Schottky characteristic is one of the important properties to determine the performance of GaN electronic devices. In this paper, we have studied how to improve the property after n$^{+}$ layer etching by ICP(Induced Coupled Plasma)-RIE(Reactive ion Etching). We have tried $N_2$radiation, annealing after $N_2$radiation, and annealing in $N_2$environment. We have found that a simple annealing method in $N_2$environment is enough to improve the Schottky characteristic for electronic device-Quality application.n.

In this paper, we describe the accommodation of the PRML technique for the high speed and high density optical disk systems, which has been very effective in the high density HDD systems. To make the PRML technique adequate for the optical disk systems, the channel modeling and the simulation are performed. Finally, the architecture has been designed and realized into an ASIC. We have focused on the differences of PRML architecture between the HDD system and the optical disk system, and the digital realization of the PLL which has been realized with analog circuits.

In this paper, we propose a wide range PLL(Phase Locked Loop) for 64X CD-ROMs & l0X DVD-ROMs. The frequency locking range of the Proposed PLL is 75MHz~370MHz. To reduce jitters caused by large VCO gain and supply voltage noise, a new V-I converter and a differential delay cell are used in 3-stage ring VCO, respectively. The new V-I converter has a 0.6V ~ 2.5V wide input range. In addition, we propose a new charge pump which has perfect current matching characteristics for the sourcing/sinking current. This new charge pump improves the locking time and the locking range of the PLL. This Chip is implemented in 0.25${\mu}{\textrm}{m}$ CMOS process. It consumes 55㎽ in worst case with a single 2.5V power supply.

본 논문에서는 이차원 위상-교정 디지털필터를 이용한 고화질 디지털 영상축소기에 관한 알고리듬과 하드웨어 구조를 제안한다. 제안된 축소기는 수직방향으로 1/32 line과 수평방향으로 1/64 pixel의 정밀도를 가진 비선형 위상 필터를 사용하여 고화질의 축소 화상을 제공한다. 최적화된 하드웨어 구조를 달성하기 위하여, 디지털필터는 shifter와 adder를 이용하여 구성한다. 마지막으로 시뮬레이션을 통해서 기존의 1/32scale[1]의 결과와 비교하여 제안된 방법의 우수성을 보인다.

The amount of data stored, processed and transmitted in the multi-media systems has been growing very fast, especially for the image data. For example, it takes 0.75Mbytes to store 512 12 pixels of 24-bit color image. A video signal with 30 frames per second will require 22.5Mbytes of storage space. To solve this problem, we need a good image compression technique. Recently, many researches on the image compression technique based on the wavelet transform are being pursued to overcome the problems of traditional JPEG. This paper describes the architecture and design of two-dimensional wavelet transform circuit. To keep the sire of the circuit small, we tried to minimize the internal storage space by using external SDRAM. This circuit was designed in Verilog-HDL, synthesized using Design Compiler and verified using Verilog-XL.

A high performance 16bit multiplier for asynchronous systems has been designed using asynchronous design methodology. The 4-radix modified Booth algorithm, TSPC (true single phase clocking) registers, and modified 4-2 counters using DPTL (differential pass transistor logic) have been used in our multiplier. It is implemented in 0.65${\mu}{\textrm}{m}$ double-poly/double-metal CMOS technology by using 6616 transistors with core size of 1.4$\times$1.1$\textrm{mm}^2$. And our design results in a computation rate exceeding 60MHz at a supply voltage of 3.3V.

Video data compression is a major key technology in the field of multimedia applications. Variable-length coding is the most popular data compression technique which has been used in many data compression standards, such as JPEG, MPEG and image data compression standards, etc. In this paper, we present memory efficient VLC decoder architecture for MPEG-2 application which can achieve small memory space and higher throughput. To reduce the memory size, we propose a new grouping, remainder generation method and merged lookup table (LUT) for variable length decoders (VLD's). In the MPEG-2, the discrete cosine transform (DCT) coefficient table zero and one are mapped onto one memory whose space requirement has been minimized by using efficient memory mapping strategy The proposed memory size is only 256 words in spite of mapping two DCT coefficient tables.

In this paper, a novel 108-bit conditional sum adder(CSA) with Energy Economized Pass-transistor Logic(EEPL) is proposed. A new architecture is adopted, in order to obtain a high speed operation, which is composed of seven modularized 16-bit CMS's and two separated carry generation block. Further a design technique based on EEPL is proposed to reduce the power consumption. With 0.65${\mu}{\textrm}{m}$ single poly, triple metal, 3.3V CMOS process, its operating speed is about 4.95㎱ and the power consumption is reduced in comparison with that of the conventional adder.

In this paper, we propose a neural network processor architecture with on-chip learning and with reconfigurability according to the data dependencies of the algorithm applied. For the neural network model applied, the proposed architecture can be configured into either SIMD or SRA(Systolic Ring Array) without my changing of on-chip configuration so as to obtain a high throughput. However, changing of system configuration can be controlled by user program. To process activation function, which needs amount of cycles to get its value, we design it by using PWL(Piece-Wise Linear) function approximation method. This unit has only single latency and the processing ability of non-linear function such as sigmoid gaussian function etc. And we verified the processing mechanism with EBP(Error Back-Propagation) model.

This paper proposes a bit allocation algorithm using adaptive bandwidth for ADSL that uses the DMT technology. In certain cases for high attenuation loops the conventional algorithms are unable to assign data bits to the higher frequency tones, due to the power spectrum mask limitation recommended by ANSI Standard, even if the total power budget is not expended. In the proposed bit allocation algorithm, adjacent empty tones that would not be used merge into single tone, then additional bits is assigned to the merged empty tones. Because additional bits is allocated, most of the available power is used. The proposed algorithm show that total bit increase in about 2~9% bits more than about conventional "water-filling" and "bit removal" algorithms and that is able to use about 93% of the available budget Power

The wavelet transform chip is implemented with Daubechies' 4 tap filter. It works at 20MHz in Field Programmable Gate array (FPGA) implementation of Quadrature Mirror Filter(QMF) Lattice Structure. In this paper, the structure contains taro-channel quadrature mirror filter, data format converter(DFC), delay control unit(DCU), and three 20$\times$8 bits real multiplier. The structures for the DFC and DCU need to he regular and scalable, require minimum number of regular, and thereby lead to an efficient and scalable architecture for the Discrete Wavelet Transform(DWT). These results present the possibility that it can be used in Digital Signal Processing(DSP) application faster than Fourier transform at small area with lour cost.

본 논문은 Booth 알고리즘을 사용하는 새로운 VQB제산기를 제안한다. 본 논문은 Macsorley의 제산 알고리즘에 기본 원리가 같은 제곱근 알고리즘을 추가하였으며, 이를 VQB 알고리즘이라고 명명하였다. 본 논문은 VQB 제산기의 두 가지 설계를 구현하였다. 하나는 계수를 사용하지 않는 설계 (A) 이며, 둘은 [1/2, 2]의 계수군을 사용하는 설계 (B)이다. 설계 (A)는 순환할때마다 2.54 비트의 부분 몫을 결정하며 설계 (B)는 2.74 비트를 결정한다. 본 논문은 VQB 제산기의 성능지표를 좌우하는 제곱근을 위주로 하여 SRT 제산기와의 비교를 시도하였다. VQB 는 처리량과 설계 노력 면에서 SRT를 앞서며, 면적과 임계지연 면에서는 SRT와 서로 견줄만한 수준이다. 표준셀 0.35㎛ CMOS 공정으로 구현될 때, 설계 (A)의 임계지연은 9.69㎱ 이며, 설계 (B)는 11.05㎱이다.

In this paper, we have proposed a testing methodology for Speed-Independent asynchronous control circuits using the self-checking property where the circuit detects certain classes of faults during normal operation. To exploit self-checking properties of Speed-Independent circuits, the Proposed methodology generates tests from the specification of the target circuit which describes the behavior of the circuit. The generated tests are applied to a fault-free and a faulty circuit, and target faults can be detected by the comparison of the outputs of the both circuits. For the purpose of efficient comparison, reachability information of the both circuits in the form of BDD's is used and operations are conducted by BDD manipulations. The identification for undetectable faults in testing is also used to increase efficiency of the proposed methodology. The proposed identification uses only topological information of the target circuit and reachability information of the good circuit which was generated in the course of preprocess. Experimental results show that high fault coverage is obtained for synthesized Speed-Independent circuits and the use of the identification process decreases the number of tests and execution time.

This Paper presents an efficient algorithm that minimizes the area of the combinational system through cell replacement. During the minimization, it maintains the circuit speed same. For the minimization, the proposed algorithm defines the criticality of each cell, based on the critical delay and the number of paths passing through the cell. Then, it visits the cells of the system, one by one, from the one with the lowest criticality, and replaces it with the minimum area cell that satisfies the delay constraint. Experimental results, using the LGsynth91 benchmark circuits synthesized by misII, show that the proposed algorithm reduces the circuit area further by 17.54% on the average without sacrificing the circuit speed.

The state assignment for a finite state machine greatly affects the delay, area, and testabilities of the sequential circuits. In order to minimize the dependencies among state variables, therefore possibly to reduce the length and number of feedback cycles, a new state assignment technique based on m-block partition is introduced in this paper. After the completion of state assignment and logic synthesis, partial scan design is performed to choose minimal number of scan flip-flops. Experiment shows drastic improvement in testabilities while preserving low area and delay overhead.

In this paper, the efficient HW/SW co-simulation method which selects the ISA model dynamically is proposed. Because the ISA models with only fixed accuracy have been used in previous co-simulation environment, it may result in bad performance in speed or accuracy. In the proposed method, the cycle accurate ISA model is used in the case that the states of the detailed system are to be inspected. In other case, instruction-based model is executed in order to accelerate the simulation speed. The proposed dynamic model selection can be done by setting the conversion point in the application code before the simulation starts. The experiment on the embedded RISC processor have been performed, and its result shows that the proposed method is more efficient than the case of using fixed ISA model.

In this paper we present an architecture, implementation, and performance evaluation of an adaptive communication system (ACS) for wide-area ATM clusters. Our approach capitalizes on thread-based programming model to overlap computation and communication and develop a dynamic message-passing environment with separate data and control paths. This leads to a flexible and adaptive message-passing environment that can support multiple flow control, error control, and multicasting algorithms. We show the performance of ACS applications and compare them with p4, PVM, and MPI applications.

Microarchitecture simulator is an important tool to verify and optimize the microarchitecture of a new microprocessor. Moreover. it can be use as a performance simulator to estimate the target microprocessor′s performance. And system software designers can use it as a software developing environment. This paper describes a "microarchitecture simulator for on-chip Multiprocessor microprocessor". It is a program-driven and cycle-based simulator that can execute simultaneous mutithreading benchmarks. We verified the microarchitecture of a new on-chip multiprocessor microprocessor with it and did performance simulations to estimate the performance of the on-chip multiprocessor microprocessor.

In this paper, we describe an implementation of the B-Link bus interface logic for a directory controller and a remote access cash controller in the SCI-based CC-NUMA multimedia server developed by ETRI . The CC-NUMA multimedia server is composed of a number of Pentium III SHV nodes and a SCI interconnection network. To communicate with remote nodes, each node has a CC-Agent which consists of a processor bus interface(PIF). a directory controller(DC), a remote access cash controller(RC), and two SCI 1ink controllers(LCs). The B-Link bus interface logic is developed for a directory controller and a remote access cash controller in order to communicate with a SCI link controller on a B-Link bus. It consists of a sending master controller a receiving slave controller, and asynchronous data buffers. And It performs a self-arbitration, a data packet transmission, a queue allocation, an early terminal ion. and a cut-through data path.

This paper describes a 32-bit RISC processor, which has instruction level compatibility with the ARM7 microprocessor. The processor is fully synthesizable, and its performance is evaluated based on 0.35-${\mu}{\textrm}{m}$ CMOS library. This paper focuses on the implementation of the processor and the reliable verification strategy ensuring the complete instruction level compatibility. The processor has successfully verified using a FPGA chip.

As the market size of multiprocessor systems for commercial applications, parallel systems, especially cache-coherent shared-memory multiprocessors that are conventionally designed for scientific applications need to be tuned in different fashion to achieve the best performance for new application area. In this paper, indepth investigation on the memory behavior which is the primary cause for performance changes were made. We chose representative benchmarks in scientific and commercial application areas. After running execution-driven simulation for bus-based cache-coherent shared-memory multiprocessors, we experienced significant differences and conclude that the systems must be carefully and differently designed to achieve the best performance when they are built for distinct applications.

Many similar class components are stored in object-storage but the object-storage has needed the retrieval function of correct component for reuse. Accordingly this paper designed the class component retrieval viewer of the object-storage by using the improved spreading activation strategy. Object-storage has made up of information of inheritance relation, superclass, subclass, and we defined the queries about each class function. Also we specified connectionist relaxation of the each class and query, finally we gained retrieval result which showed highest activation value order of class component information including the query function.

Woo[8]proposed dual-token based fault-tolerant scheduling algorithm in multiprocessor environment for resolving the problem of old systems that have a central dispatcher processor. However, this algorithm does not present token allocation algorithm in detail when central dispatcher processor has failed. In this paper, we propose a fault detection algorithm and processor selection algorithm for token allocation when central dispatcher processor has failed.

The primary aim of this paper is to introduce and illustrate a radial basis function (RBF) modeling approach fur software module characterization, as an alternative to current techniques. The RBF model has been known to provide a rich analytical framework fur a broad class of so-called pattern recognition problems. Especially, it features both nonlinearity and linearity which in general are treated separately by its learning algorithm, leading to offer conceptual and computational advantages. Furthermore, our new modeling methodology fer determining model parameters has a sound mathematical basis and showed very interesting results in terms of model consistency as well as performance.

본 논문은 복잡 적응 시스템의 분석 및 모델링을 위해, 인공생명의 기본 패러다임인 셀룰라 오토마타를 선택하여, 무정형의 구조를 가지며 투명한 자료 전파 특성을 갖는 셀룰라 신경 회로망의 설계하고 개발하는데 중점을 두었다. 우선, 신경 회로망의 불규칙한 구조를 발생학적으로 다루어 무정형의 은닉층을 생성하고, 다윈의 진화론을 적용하여 구조적 진화 및 선택을 통해 최적화된 신경 회로망을 설계하였다. 주변 셀의 상태를 감지하여 자신의 상태를 수정해나가는 방식의 셀룰라 오토마타의 투명한 신호 전파 모델로 자료 및 오차의 역전파에 적용하도록 고안하였고, 라마르크의 용불용설을 활용한 오차의역전파 학습 알고리즘을 유도하였다. 이러한 복잡 적응계의 학습 과정을 유도하여 시뮬레이션에서 그 타당성을 입증하였다. 시뮬레이션에서는 신경 회로망의 XOR 문제와 다중 입력 다중 출력 함수에 대한 근사화 문제를 풀었다.

In this paper, we propose a new object representation method and matching algorithm for object recognition using a 3-fingered robot hand. Each finger tip can measure normal vector and shapes of a contacting surface. Object is represented by the inter-surface description table where the features of a surface are described in the diagonal and the relations between two surfaces are in the upper diagonal. Based on this table, a fast and the efficient matching algorithm has been proposed. This algorithm can be applied to natural quadric objects.

Genetic algorithm is well known as the efficient algorithm which can solve a difficult problem. Network design considering reliability is NP-hard problem with cost, distance, and volume. Therefore genetic algorithm is considered as a good method for this problem. This paper suggests the reliable network which can be constructed with minimum cost using genetic algorithm and the rank method based on reliability for improving the performance. This method shows more excellent than existing method and confirms the result through simulation.

In this paper, we propose a method of unconstrained handwritten numeral recognition using image dithering and multiple modular MLPs. The set of sample numeral patterns is subdivided into clusters which are extended by their radius. On each extended cluster, we constructed MLPs network as the expert recognizer of corresponding cluster. The gating network is also trained by an MLPs to weigh the outputs of expert MLPs. In training and test phase of the recognizer, we utilize the multiple dithered numeral images and the combination of the outputs for corresponding dithered images. Experimental results show that our recognition method works very well.

We present an efficient face recognition method that is robust to illumination changes. We named the proposed method as SKKUfaces. We first compute eigenfaces from training images and then apply fisher discriminant analysis using the obtained eigenfaces that exclude eigenfaces correponding to first few largest eigenvalues. This way, SKKUfaces can achieve the maximum class separability without considering eigenfaces that are responsible for illumination changes, facial expressions and eyewear. In addition, we have developed a method that efficiently computes beween-scatter and within-scatter matrices in terms of memory space and computation time. We have tested the performance of SKKUfaces on the YALE and the SKKU face databases. Initial Experimental results show that SKKUfaces performs greatly better over Fisherfaces on the input images of large variations in lighting and eyewear.

Usually, more reference signatures result in better performance in signature verification. However, registering .many signatures may be a tedious work for users, so algorithms that use less signatures for the registration without increasing error rate is needed. In this paper, we find the features such as pen-down duration, the number of locally minimum velocity points, and the number of locally maximum curvature points. Then we find the relationship between these features and the optimal decision boundary. We apply this relationship in deciding threshold for signature verification. Experimental results show that the method using three reference signatures has almost same error rate as algorithms with many references.

In this paper, we present a solution for combining multiple neural networks. Each neural network is trained with different features. And the neural networks are combined by four methods. The recognition rates by four combination methods are compared. The experimental results for handwritten digit recognition shows that the combination at hidden layers by single layer neural network is superior to any other methods. The reasons of the results are explained.

In the paper, we discussed an investigation for Improvement of control precision by reasonably introducing difference and integral of error in Fuzzy control

In this paper, we implement and construct a kernel on handhold systems. The goal of this project is to develop issues related to the development of small devices: embedded kernel, power management, user interface issues, networking, and the development of applications for small devices. We explain basic system configuration, kernel activity, device drivers and developing environment in this paper. We also explain detail scheduler activity.

In this paper, we present a real-time hand gesture recognition system that controls motion of a human avatar based on the pre-defined dynamic hand gesture commands in a virtual environment. Each motion of a human avatar consists of some elementary motions which are produced by solving inverse kinematics to target posture and interpolating joint angles for human-like motions. To overcome processing time of the recognition system for teaming, we use a Fuzzy Min-Max Neural Network (FMMNN) for classification of hand postures

In this paper we propose an efficient content-based image retrieval method using the color and wavelet based features. The color features are extracted from color histograms of the global image and the wavelet based features are extracted from the invariant moments of the high-pass band image through the spatial-frequency analysis of the wavelet transform. The proposed algorithm, called color and wavelet features based query(CWBQ), is composed of two-step query operations for efficient image retrieval: the coarse level filtering operation and the fine level matching operation. In the first filtering operation, the color histogram feature is used to filter out the dissimilar images quickly from a large image database. The second matching operation applies the wavelet based feature to the retained set of images to retrieve all relevant images successfully. The experimental results show that the proposed algorithm yields more improved retrieval accuracy with computationally efficiency than the previous methods.

Introduction of digital communication network such as Integrated Services Digital Networks(ISDN) and digital storage media have rapidly developed. Due to a large amount of image data, compression is the key techniques in still image and video using digital signal processing for transmitting and storing. Digital image compression provides solutions for various image applications that represent digital image requiring a large amount of data. In this paper, the proposed DWT(Discrete Wavelet Transform) filter bank is consisted of simple architecture, but it is efficiently designed that a user obtain a wanted compression rate as only input parameter. If it is implemented by FPGA chip, the designed encoder operates in 12MHz.

In this paper, we propose the adaptive Odd/Even Multi-shell Median Filter(adaptive O/E MMF) to improve the defect that Modified Multi-shell Median Filter(MMMF) can not recover missing lines of vertical and cross direction. This filter uses odd/even multi-shells and new proposed threshold strategy The performance of the proposed filter is evaluated over image 'airfield 'by using MATLAB. As the proposed threshold strategy eliminate the number of redundant replacement, it suppresses impulse noise and recovers missing lines.

This paper presents a PCI (Peripheral Component Interconnect) controller embedded in a multimedia processor, called FLOVA (FLOating point VLIW Architecture), targeting for 3D graphics applications. Fast I/O interfaces are essential for multimedia processors which usually handle large amount of multimedia data. Therefore, in FLOVA, PCI bus is adopted for I/O interface due to fast burst transaction. However, there are several problems in implementation and verification to use burst transaction of PCI. It is difficult to handle data transaction between two units which have two different operating frequency. FLOVA has more higher operating frequency about 100MHz than that of PCI local bus and it makes lower utilization of FLOVA bus. Also, traditional simulation is not sufficient for verification of PCI functionality. In this paper, we propose buffering schemes to implement the PCI controller with wide bandwidth and high bus utilization. Also, this paper shows how to verify the PCI controller using real PCI bus environments before its fabrication.

Recently, as increasing population of internet, the larger one of required facts is solution for access speed, that transmission performance. ADSL system can provide the best application to resident in low cost, flexible approach. In this paper, for DMT line code that is one of ADSL modulation/demodulation signal processing methods, transmission performance and characteristic are discussed as studies and analysis through computer simulation using MATLAB. We made results with practising simulation using parameters based on ANSI standard Tl .413 Iusse2.

Inspection of BGAs presents several challenges for modem measurement equipment. No only must these systems be fast and accurate, they must deal with the special challenges presented by very small shiny metal spheres. For accurate measurement, we propose an algorithm which fits for estimating the accurate ball height using 2-D curve-fitting algorithm. The real boundary between two adjacent pixels and the real ball diameter are measured with subpixel accuracy Experimental results show that the proposed method calculates the ball height and diameter with subpixel accuracy and is robust in local noise with low measurement error.

I here are many kinds of method to compress data. To very simple methods from very complex methods, a kind is various. In this study, the simplest form of the Tolerance-Comparison method, zero-order method is used. Using this method, despite using low speed CPUs, it is possible to compress real time data. So this method is suitable for ECG holler system. In this study, to complement zero-order method, it is needed to develop prediction technique and to research ways to apply the technique.

In this paper, we propose a non-invasive method to estimate blood velocity from the real medical images. To measure the magnitude and direction components associated with the blood velocity, we apply the optical flow analysis algorithm. It is demonstrated that the accuracy of the blood velocity estimate could possibly be increased by segmenting the optical flow region. We call this the Region Optical Flow(ROF) algorithm. We carried out some preliminary experiments using the aorta medical images, and corresponding regional optical flow diagrams are provided.

In spite of advances in image resolution and film contrast, check screen/film mammography remains one of diagnostic imaging modality where the image interpretation is very difficult. For the enhancement of film mammography, in this paper, dyadic wavelet transform is introduced. An unsharp masking technique is proposed and performed in wavelet domain. In addition, simple nonlinear enhancement and a denosing stage that preserves edges using wavelet shrinkage are computed into this technique. In this paper. we propose a new method for the gain setting of nonlinear enhancement and show result and comparison.

Abstract - In this paper, a segmentation method for brain Magnetic Resonance(MR) image using region clustering technique with statistical distribution of gradient image and fuzzy rules is described. The brain MRI consists of gray matter and white matter, cerebrospinal fluid. But due to noise, overlap, vagueness, and various parameters, segmentation of MR image is a very difficult task. We use gradient information rather than intensity directly from the MR images and find appropriate thresholds for region classification using gradient approximation, rayleigh distribution function, region clustering, and merging techniques. And then, we propose the adaptive fuzzy rules in order to extract anatomical structures and diseases from brain MR image data. The experimental results shows that the proposed segmentation algorithm given better performance than traditional segmentation techniques.

Automatic human face detection in a complex background is one of the difficult problems. In this paper, we propose an effective and robust automatic face detection approach that can locate the face region in natural scene images when the system is used as a pre-processor of a face recognition system . We use two natural and powerful visual cues, the skin color and the eyes. In the first step of the proposed system, the method based on the human skin color space by selecting flesh tone regions using normalized r-g space in color images. In the next step, we extract eye features by calculating moments and using geometrical face model. Experimental results demonstrate that the approach can efficiently detect human faces and satisfactory deal with the problems caused by bad lighting condition, skew face orientation.

In this paper we propose a 3D emotional expression method using a comic model for effective sign-language communications. Until now we have investigated to produce more realistic facial and emotional expression. When representing only emotional expression, however, a comic expression could be better than the real picture of a face. The comic face is a comic-style expression model in which almost components except the necessary parts like eyebrows, eyes, nose and mouth are discarded. We represent emotional expression using Action Units(AU) of Facial Action Coding System(FACS). Experimental results show a possibility that the proposed method could be used efficiently for sign-language image communications.

We propose a face tracking algorithm using skin-color based segmentation and a robust Hausdorff distance. First, we present L＊a＊b＊ color model and face segmentation algorithm. A face is segmented from the first frame of input video sequences using skin-color map. Then, we obtain an initial face model with Laplacian operator. For tracking, a robust Hausdorff distance is computed and the best possible displacement t. is selected. Finally, the previous face model is updated using the displacement t. It is robust to some noises and outliers. We provide an example to illustrate the proposed tracking algorithm in video sequences obtained from CCD camera.

This paper proposes a high-speed texture mapping algorithm and apply it for the realtime face animation. The mapping process devide into pixel correspondences, Z-buffering, and pixel value interpolation. Pixel correspondences and Z-buffering are calculated exactly through the algorithm. However, pixel values interpolation is approximated without additional calculations. The algorithm dramatically reduces the operations needed for texture mapping. Only three additions are needed in calculation of a pixel value. We simulate the 256$\times$240 pixel facial image with about 100 pixel face width. Simulation results shows that frame generation speed are about 60, 44, 21 frames/second in pentium PC 550MHz, 400MHz, 200MHz, respectively,

We design a keyframe editor of arms and hands for 3D sign-language animation using inverse kinematics. In the previous study, we acquired only the joint angles of two arms after selecting arbitrarily the shapes of hands. In this paper, both joint angles of arms and hands are calculated by the same transformation matrix of the inverse kinematics. In the method, the design window of arm gestures can be converted into that of hand shapes by clicking a button. Experimental results show a possibility that the proposed method could be used for building up the sign-language communication dictionaries.

In this paper, a method for extracting the fingerprint regions and the table from fingerprint document which is the size of A4 including ten fingerprints images in a table is presented. The extraction of each fingerprint region is carried out by segmenting the foreground fingerprint region using a block filtering method and detecting its center point. The table extraction, by detecting a horizontal line using line tracing, and detecting a vertical line by its orthogonal equation. Here, T-shaped mask is proposed for finding the starting points of the vertical line intersecting horizontal line by the form of 'T'. Experimental results show above 95% correct rate of extracting the fingerprint region and table.

This paper proposes an hybrid person identification algorithm utilizing finger crease pattern and finger thickness profiles. We have observed that by adding finger thickness profiles as a feature vector, we could improve the performance of the person identification system utilizing only finger crease pattern. We presented the comparative evaluation of the proposed algorithm in detail.

In this paper, we present an optimal hardware implementation for preprocessing of a person identification algorithm utilizing vein pattern of dorsal surface of hand. For the vein pattern recognition, the computational burden of the algorithm lies mainly in the preprocessing of the input images, especially in lowpass filtering. we could reduce the identification time to one tenth by hardware design of the lowpass filter compared to sequential computations. In terms of the computation accuracy, the simulation results show that the CSD code provided an optimized coefficient value with about 91.62% accuracy in comparison with the floating point implementation of current coefficient value of the lowpass filter. The post-simulation of a VHDL model has been performed by using the ModelSim$^{TM}$. The implemented chip operates at 20MHz and has the operational speed of 55.107㎳.㎳.

In this paper, we will show the brief technical specification of HPEG-4 International Standard that is reached at the final stage and the movement of multimedia industry according to it. As a result of MPEG-4 standardization activities, we would like to give you our opinion on the use of the MPEG-4 technologies for the coming information society in near future.

In this paper we present a color image segmentation algorithm based on statistical models. A novel deterministic annealing Expectation Maximization(EM) formula is derived to estimate the parameters of the Gaussian Mixture Model(GMM) which represents the multi-colored objects statistically. The experimental results show that the proposed deterministic annealing EM is a global optimal solution for the ML parameter estimation and the image field is segmented efficiently by using the parameter estimates.

This paper presents a new shape segmentation algorithm. The procedure to achieve complete segmentation consists of two steps : the first step is mapping shape into two dimension by the using Distance Transform, the second step is partitioning the region by using the Watershed algorithm. As a application of the proposed algorithm, we perform the matching experiment for several objects by the use of segmented region. Simulation results demonstrate the efficiency of the proposed method, and the method has scale, rotation, and shift invariant properties.

Padding is a technique that enables applying conventional discrete cosine transform to encode boundary blocks of arbitrarily shaped objects by assigning imaginary values to the pixels that are not included in the object. Padding prevents the increase of high frequency DCT coefficients. However, in some boundary blocks, too many padded pixels are coded due to a small portion of object pixels. To reduce the number of padded pixels and to improve coding efficiency, we propose a block merging method for texture coding. The proposed mothed searches the shape information of boundary blocks and excludes the 4$\times$4 pixels of 8$\times$8 blocks if all the 4$\times$4 pixels are in the background region, and merges the remained 4$\times$4 pixels into new 8$\times$8 blocks. Experimental results show that our proposed method yields a rate-distortion gain about 0.5~1.6㏈ compared to conventional padding method, LPE

In order to retrieve the rotated image within database by the content based image retrieval system, the algorithms with rotation robustness is usually applied in the procedure of the feature extraction. In that case, it requires much calculation time for feature extraction and much indexed data for feature indexing. Thus. in this paper. we propose the rotation robust algorithm using the block variance of the projected vector. The algorithm does not require additional calculation for feature extraction and is executed within query time by comparing the extracted data. Proposed method can be processed through database including various size of images with shape information and executed with fast response time in implementation.

This paper concentrates on an experimental results on visual only recognition tasks using an image transform approach and HMM based recognition system. There are two approaches for extracting features of lipreading, a lip contour based approach and an image transform based one. The latter obtains a compressed representation of the image pixel values that contain the speaker's mouth results in superior lipreading performance. In addition, PCA(Principal component analysis) is used for fast algorithm. Finally, HMM recognition tasks are compared with the another.

Matching is a key problem in computer vision, image analysis and pattern recognition. In this paper a multiscale image matching algorithm by wavelet local extrema is proposed. This algorithm is based on the multiscale wavelet transform of the curvature which can utilize both the information of local extrema positions and magnitudes of transform results. This method has advantages in computational cost to a single scale image matching. It is also rotation-, translation-, and scale-independent image matching method. This matching can be used for the recognition of occluded objects.

In this paper, we propose an image retrieval system using the MBCM(Modified Borda Count method) in CME(Combining Multiple Experts). It combines color-, shape- and texture-based retrieval sub-systems. CME method can complementarily combine results of each retrieval system, which uses different features. There are some problems when the Borda count method in pattern recognition is applied to image retrieval. Thus, we propose a modified Borda count method to solve these problems. In the experiment, our method reduces false positive errors and produces better results than that of each retrieval module that uses only one feature.

In this paper, we propose a fast object-tracking algorithm in a moving picture. The proposed object-tracking algorithm is based on a projection scheme. More specifically, to alleviate the computational complexities of the previous motion estimation methods, we propose to use the projected row and column 1-D image data to extract the motion information. Experimental results show that the proposed method can detect the motion of an object fairly well with reduced computational time.

This Paper proposes the simple and efficient image retrieval algorithm using subregional texture features. In order to retrieve images in terms of its contents, it is required to obtain a precise segmentation. However, it is very difficult and takes a long computing time. Therefore. this paper proposes a simple segmentation method, which is to divide an image into high and low entropy regions by using Picture Information Measure (PIM). Also, in order to describe texture characteristics of each region, this paper suggest six different texture features produced on the basis of co-occurrence matrix. For an image retrieval system, a normalised correlation is adopted as a similarity function, which is not dependent on the range of each texture feature values. Finally, this proposed algorithm is applied to a various images and produces competitive results.

In this paper, we proposed several scene analysis algorithms. These algorithms using image difference and histogram operate on the sequence of DC coefficient which is extracted from Motion JPEG or MPEG without full-frame decompression. Since DC sequence has the most information of full frame while it has reduced data. Experimental results show less than 1/64 of full frame analysing complexity and exactly analyze scene changes and extract key frames.

In this paper, we propose wavelet transform image compression method such that an image is decomposed into multiresolutions using biorthogonal wavelet transform with linear phase response property and decomposed subbands are classified by maximum classification gain. The classified data is quantized by allocating bits in accordance with classified class informations within subbands through arbitrary set bit allocation algorithm. And then, quantized data in each subband are entropy coded. The proposed coding method is that the quantized data perform shuffling before entropy coding in order to remove sign bit plane. And the context is assigned by maximum correlation direction for bit plane coding.

A new approach is presented for estimating depths of defocused objects which are at distances by camera motions. An ordinary camera is used for obtaining defocused images in order to propose a coarse method with a potential. This method, therefore, requires only a few camera parameters, the amount of camera motions and defocused images that mean the sizes of defocused images in itself. We use the median filter as a fitting method for estimating depths of useful accuracy with relatively simple scheme. Experiments with real images show that depths of objects can be estimated concurrently although there are several objects in an image.

In this paper, a new autofocusing technique which is resistive to noise generated by the CCD of video cameras is proposed. In the proposed scheme, the frequency selective weighted median (FSWM) filter is utilized to estimate the degree of focus and the fast hill-climbing search (HCS) strategy is exploited to determine the best focused image. Since the FSWM filter can not only extract high frequency components from the image, but also eliminate impulsive noise, the proposed autofocusing method employing the FSWM criterion function can estimate the degree of focus precisely. Furthermore, the proposed real-time HCS algorithm enables the video camera to continuously focus on dynamic images. Experimental results demonstrate that the proposed technique outperforms existing techniques by enhancing the accuracy of the focus value of the video camera without the influence of noise.

This paper describes a distance estimation method of object's motion in soccer image sequence by tracking field features. And we quantitatively evaluate the estimation accuracy We suppose that the input image sequence is taken with a camera on static axis and includes only zooming and panning transformation between frames. Adaptive template matching is adopted for non-rigid object tracking. For background compensation, feature templates selected from reference frame image are matched in following frames and the matched feature point pairs are used in computing Affine motion parameters. A perspective displacement field model is used for estimating the real distance between two position on Input Image. To quantitatively evaluate the accuracy of the estimation, we synthesized a 3 dimensional virtual stadium with graphic tools and experimented on the synthesized 2 dimensional image sequences. The experiment shows that the average of the error between the actual moving distance and the estimated distance is 1.84%.

In this paper, we consider the problem of finding the depth of a object in two images taken with cameras. For solving this problem, we introduce a spherical concave mirror model. First, a virtual concave mirror is assumed, and then a scene is obtained by camera at two different position which are on the surface of the mirror. The depth of object is calculated from two scenes by using the spherical-mirror equation. The algorithm has been tested on a real scene containing several objects, and showed that it is more useful for farther object.

In this paper, color coordinate system transformation based visual servo controller has been considered. Mobile robot always has a position error and an orientation error resulted from wheel slipping etc.. Even more, the errors have accumulative properties. So feedback from environments is important. In this paper, by using color model faster land mark extraction can be achieved. And the global position and the orientation of mobile robot can be known by only two land marks positions in image coordinate system. Finally, the adoption of visual information in path tracking problem makes visual servo control.

We present a robust scheme of detecting obstacles such as vehicles, human beings, and other artificial structures that may cause serious traffic accidents in the nighttime driving. Obstacle regions are detected by the evidential reasoning rules that combine the isolated regions obtained by the phase-directed edge-linking and the hot evidence information. Preliminary experimental results show that the performance is robust to nighttime infrared scenes having various types of obstacles

In this Paper we show the LCD simulator for defect inspection using image processing algorithm and neural network. The defect inspection algorithm of the LCD consists of preprocessing, feature extraction and defect classification. Preprocess removes noise from LCD image, using morphology operator and neural network is used for the defect classification. Sample images with scratch, pinhole, and spot from real LCD color filter image are used. The proposed algorithms show that defect detected and classified in the ratio of 92.3% and 94.6 respectively.

스테레오 물체 추적기는 좌. 우측 카메라의 스테레오 입력 영상에서 이동 물체의 주시각을 제어하면서 자동으로 추적 물체가 항상 영상의 중앙에 위치하도록 제어해야 한다. 본 논문에서는 복잡한 배경이 존재하고 카메라가 움직이는 경우 스테레오 물체 추적을 위한 방법으로 블록 정합 알고리즘(BMA)으로 추적 물체와 배경을 분리하고, JTC를 이용해 주시각 및 팬/틸트 제어 값을 구하여 좌, 우측 카메라를 제어하는 스테레오 자동 물체 추적 시스템을 제시하였다. 추적결과 배경잡음에 상관없이 적응적으로 작용하여 정확히 이동 물체의 위치를 스테레오로 추적할 수 있었다.

본 논문에서는 음성신호처리 기법을 이용하여 장애음성을 진단, 개선하는 데 필요한 다양한 신호처리방법에 대하여 다루고자 한다. 음성장애중 성대장애를 중심으로 신호에 나타나는 현상과 이를 이용한 신호처리 방법들을 소개하며 응용사례로 음성을 이용한 성대질환의 진단에 관한 내용을 소개한다.

This paper investigates the varying characteristics of the performance degradation resulting from the different combination of wordlength in fixed-point implementation of recursive sinusoidal transform. The performance degradation is analytically derived in the form of noise-to-signal power ratio. The best wordlength combination is shown to be the equal length distribution of the given number of bits between the transform coefficients and the data. The analysis results are also verified through the computer simulations.

In this study, We derived Recursive Least Squares(RLS) algorithm with adaptive maximum -likelihood channel estimate for digital pulse amplitude modulated sequence in the presence of intersymbol interference and additive white Gaussian noise. RLS algorithms have better convergence characteristics than conventional algorithms, LMS Least Mean Squares) algorithms.

In this paper we implement MP3 encoder based on integer operations. To implement MP3 encoder presented in ［1］, floating-point operations are required. But we devise an MP3 encoding method which is based on integer operations. To verify the method presented in this paper, we implement MP3 encoder using ARM processor. In this paper we present the method to change floating point operations into integer operations, and the ARM assembly programming technique to implement fast MP3 encoder. The MP3 encoder implement using integer processor consumes less power than the encoder implemented using floating-point processor. So the encoder implemented in this paper is suitable lot portable applications which requires low power consumption.

In this paper, we review the conventional speaker verification algorithm and present the text-dependent speaker verification system for application over telephone lines and its result of experiments. We apply blind-segmentation algorithm which segments speech into sub-word unit without linguistic information to the speaker verification system for training speaker model effectively with limited enrollment data. And the World-mode] that is created from PBW DB for score normalization is used. The experiments are presented in implemented system using database, which were constructed to simulate field test, and are shown 3.3% EER.

현대 사회의 컴퓨터 사용자 계층은 점점 그 범위와 수가 커지고 있다 이러한 추세는 앞으로도 계속 증가할 것이다. 따라서 많은 사람들은 더 편리하고 익히기 쉬운 컴퓨터의 사용법을 원하고 생활속에서 더 많이 컴퓨터를 활용하기를 원한다. 그러므로 인간에게 가장 친숙한 음성을 이용함으로써 이런 사용자들의 필요를 충족시킬 수 있을 뿐 아니라 사용자가 쉽게 접할 수 있도록 할 수 있다. 그러므로 본 논문의 목적은 이러한 상황에서 인간과 기계와의 인터페이스를 인간의 기본적인 의사소통 수단인 음성을 이용하여 보다 빨리 작업 할 수 있게 하는 취지에 있다. 기존의 인식알고리즘은 그 복잡성이 높을수록 인식률은 증가하나 계산시간이 많이 걸린다는 단점이 있다. 이러한 계산시간의 증가는 윈도우환경의 컴퓨터 사용시 다른 프로그램의 실행에 지장을 줄 수 있다. 따라서 인식률은 증가시키면서 인식 시간은 감소시킬 수 있는 방법들이 필요하다. 본 논문에서는 컴퓨터 사용시 쓰이는 명령어를 기본으로 하여 보다 빠른 인식 처리를 수행하기 위해 기준 패턴의 후보자를 선정하는 방법을 제안한다

In this paper, we propose a MLP neural network architecture and feature extraction for Korean syllable recognition. In the proposed syllable recognition system, firstly onset is classified by onset classification neural network. And the results information of onset classification neural network are used for feature selection of imput patterns vector. The feature extraction of Korean syllables is based on sonority. Using the threshold rate separate the syllable. The results of separation are used for feature of onset. nucleus and coda. ETRI's SAMDORI has been used by speech DB. The recognition rate is 96% in the speaker dependent and 93.3% in the speaker independent.

In this paper, we presents a method to control prosody of the synthetic speech using sampling rate conversion technique. In prosody control, the conventional methods perform overlap and add. So the synthetic speech has a distortion and the voice quality is not satisfied. Using sampling rate conversion technique, we can get high Qualify of the synthetic speech. Also we can control various talking speeds according to speaker's patterns.

This paper describes design of equalizer chips of the read channel for high-density hard-disk drives. In order to meet increasing need of hard-disk drives, the read channel incorporates various PRML schemes. They require proper equalization to implement the efficient hardware of Viterbi decoders. This paper describes EPR-IV equalization for the read channel and a 200MHz analog FIR filter chip is presented which utilizes the sampled analog signal processing efficiently.

This paper describes a 10-bit 75-MHz CMOS current-mode DAC designed for 0.8${\mu}{\textrm}{m}$ double-poly double-metal CMOS technology. This D/A converter is implemented using a current cell matrix that can drive a resistive load without output buffer. In the DAC. a current source is proposed to reduce the linearity error caused by the threshold-voltage variations over a wafer and the glitch energy caused by the time lagging, The integral and differential linearity error are founded to be within $\pm$0.35 LSB and $\pm$0.31 LSB respectively. The maximum conversion rate is about 80 MS/s. The total power dissipation is 160 ㎽ at 75 MS/s conversion rate.

This paper presents an analysis of the chaotic behavior in the discrete-time chaotic generator fabricated by CMOS technology. An approximated empirical equation is extracted from the measurement data of a nonlinear function block. Then the bifurcation diagram and Lyapunov exponent and time waveforms and frequency responses of the chaotic generator are calculated and simulated. And results of experiments in the chaotic circuit with the $\pm$2.5V power supply and clock rate of 10KHz are shown, and analysed.

This Paper presents the design, fabrication, analysis of the measured date of a voltage controlled oscillator(VCO) for the application of Personal Communication Systems. Main VCO circuit consists of self biased emitter resonating circuit with microstrip line resonator on FR4 epoxy substrate. A varactor diode is used for 90MHz frequency tuning with center frequency of 1635MHz Phase noise of -114.67㏈C/Hz at 100KHz off set has been achieved with 3.3 V supply. The size of the fabricated VCO circuit is 1.25 cm$\times$ 1.25 cm.

In this paper, robust vibration control of a one-link flexible robot arm based on variable structure system is discussed. We derive dynamic equations of it using a Lagragian assumed modes method based on Bernoulli-Euler beam theory. The optimal sliding surface is designed and the problem of chattering is also solved by the adoptation of a continuous control law within a small neighborhood of the switching hyperplane.

In this paper, an algorithm of fault tolerant gaits for a quadruped robot is proposed for the purpose of tolerating a locked joint failure. The robot can continue its walking after a locked failure occurs to a joint of a leg by the proposed algorithm. In particular, a periodic gait is proposed as a special form of the proposed algorithm and its existence and efficiency are analytically proven.

The goal of this paper is to provide a Graphic man-machine interface that can be used to control multiple robots simultaneously. The proposed GUI scheme gave emphasis on making multiple robots Perform the cooperative works, maintaining a given formation. It controls multiple robots in two different modes. : a group mode and a individual mode. In the group mode, a common goal position and formation are delivered to individual robots at the same time, and in the individual mode one robot is selected. o increase the efficiency of the interface, a time scheduler is provided. The experimental results are included.

In this paper, a real-time control system for robot manipulator is implemented using real-time operating system with capabilities of multitasking, intertask communication and synchronization, event-driven, priority-driven scheduling, real-time clock control, etc. The hardware system with VME bus and related devices is developed and applied to implement a dynamic learning control scheme for robot manipulator. Real-time performance of the proposed dynamic learning controller is tested for tasks of tracking moving objects and compared with the conventional servo controller.

For that the attitude control performance test of the satellite, dynamic analysis of satellite structure performed in reference with KOREASAT, and the equation of motion of rigid bodies was derivated. For attitude stability, Lyapunov's stability theorem and state space expression were applied to dynamic equation of satellite. To prove efficiency of our method, simulations are performed and result are shown.

The previous LQ-servo PI design methods have some serious design problems happened from the frequency matching of the maximum and minimum singular values of loop transfer function at both low and high frequency regions on the Bode plot. To solve these problems, this paper proposes a new design technique based on the inverse-optimal control and convex optimization.

This paper concerns a development of LQ-servo PI controller design on the basis of time-domain approach. This is because the previous design techniques developed on the frequency-domain is not well suited to meet the time-domain design specifications. Our development techniques used in this paper is based on the convex optimization methods including Lagrange multiplier, dual concept, semidefinite programming.

A GA-based optimization technique is adopted in the paper to obtain optimal future control inputs for predictive control systems. For reliable future predictions of a process, we identify the underlying process with an NNARX model structure and investigate to reduce the volume of neural network based on the Lipschitz index and a criterion. Since most industrial processes are subject to their constraints, we deal with the input-output constraints by modifying some genetic operators and/or using a penalty strategy in the GAPC. Some computer simulations are given to show the effectiveness of the GAPC method compared with the adaptive GPC algorithm.

This study is to increase capability of the DC/DC converter (for PCS) in miniaturizing, stabilizing by locating an inductor with the structure of multi layer on to the glass/ceramic circuit board. When the DC/DC converter is stimulated. the characteristic operation of PWM switching circuit, losses. output power to input power, stability, efficiency and interfaces inside of control circuit and convener circuit are to be distinguished. The process would make it able to develop the techniques of designing and manufacturing of the converter of next generation.

In this paper, Flyback type DC/DC Switching Converter was designed, analyzed and fabricated. Worst Case Analysis(WCA) was peformed with Mathcad program and presents circuit simulation results for the in-rush current limit circuit. The value of the maximum OFF voltage stress is 131.84V, it is less than device specification(200V). The switching frequency(nominal case) and duty cycle at the wont case analysis are 75KHz and 34.62%, respectively. The maximum in-rush current presents 0.5A Those results show a possibility for use in space

A 30Watt inverter with 300: 1 dimming capability for high luminance, one cell, surface discharge plasma light source for LCD backlight was designed and tested. It was possible to achieve 300:1 dimming control by using the push-pull type inverter with burst-mode dimming control. The surface discharge plasma light cell with luminance of more than 5, 260 cd/$m^2$ was successfully operated.

In this paper, a simple SR method of AC motor has introduced. The method achived by appling the Pulse-Width Modulation(PWM) method to control the ON and OFF time of motor. The method is simple, practicable and has no problem of shift and out of control which is existed in SR method of SCR.

In this paper, we introduce the concept of a HAPS(High Altitude Platform Station) system which is expected to be a next generation communication system and suggest several error correcting codes to provide high quality services. Since a HAPS system encounters serious signal attenuation due to rain and scattering in the air, concatenated codes which have a high coding gain is considered to be a proper error correcting method. In this paper, we provide performance analyses result of two candidate coding schemes for a HAPS. The first one is a conventional concatenated coding scheme, and the second one is a iterative decoding method known as Turbo Codes.

Direct-Sequence code-division multiple access(DS/CDMA) is considered by many to be a promising technology for future wireless communication networks. In this paper, we report new analysis for probability of BPSK CDMA hypothesis test in jointly distributed AWGN Rayleigh-fading received signal. In previous method, analysis is performed on AWGN or Rayleigh-faded signal in separately. In this paper, we propose model for hypothesis test system of the AWGN Rayleigh-faded received signal.

This paper investigates the performance of the hyperbolic position location(PL) technique in CDMA system. Hyperbolic PL systems are such technology that can provide accurate PL information using the existing cellualr/PCS infrastructure and without requiring additional hardware/software implementation within the mobile unit. The channel simulation is obtained by applying AWGN and multipath fading. The effect of the mobile position within the cell and the number of base stations on the accuracy of the hyperbolic PL technique is investigated.

This paper presents a new timing structure for real time communications and its performance analysis. The cycle time consists of several "one time slot" which may be an interval defined by a synchronous traffic part followed by an asynchronous traffic part. If a station receives a token within a synchronous interval, it transmits its synchronous message if any, otherwise it may transmit an asynchronous message. This scheme is different from usual allocation schemes which divide one cycle into alternating synchronous and asynchronous subslots. This protocol is designed to prevent low priority messages from delaying too much due to lots of high priority messages. We propose the algorithm and show its justification by simulation.

This paper presents design of AGC(Automatic Gain Control) and DC offset remover suitable for cable modem which makes use of QAM(Quadrature Amplitude Modulation) scheme. Since QAM has multi-level signal characteristic, for high-order QAM, the constellation is dense and the distance of decision boundary between adjacent symbols is short. So AGC and DC offset remover must be designed optionally for preventing performance degradation. AGC is designed into feedback type and is related to the STR(Symbol Timing Recovery)and Paff interpolation algorithm. Whereas AGC need to perform average power detection during many symbols by comparison with the reference power, DC offset remover uses only the instant polarity decision such that simple implementation can be achieved with good performance. Though the AGC and DC offset remover are simulated here only for 256 QAM scheme for convenience'sake, it can be applied to other multi-level QAM or PSK modulation scheme.

This paper gives channel estimation of W-CDMA reverse link using 2-point second-order algorithm over Rayleigh fading channels. The proposed algorithm is compared with the existing interpolation algorithms, i.e., WMSA, linear and second-order Gaussian interpolation, by obtaining HER performance through computer simulations. The BER performance of 2-point second-order interpolation is superior to other algorithms in fading channels. The proposed algorithm also has relatively-simple structure and similar processing delay in comparison to the existing algorithm, Therefore, this algorithm is more suitable for high speed mobile communication environments.

This paper describes a direct digital frequency synthesizer using the CORDIC algorithm, which can be implemented efficiently for a digital sinusoid synthesis. To optimize the hardware design parameters, we perform numerical analysis of the quantization effects for the CORDIC-based architecture. A pipelined architecture is employed to obtain a high data throughput,. We estimate and summarize its hardware costs for a variable accuracy, and a CORDIC-based architecture for 9 bit accuracy is emulated in FPGA.

A principle requirement and technical standardization for numbering plan is required to B-lSDN network planning. Especially, internetworking high speed network with other conventional networks like PSTN, PSDN and ISDN is generally considered for integration. This paper describes the numbering plan for operation between internet and ATM. And based on the ITU-U specification, numbering plan is compared between conventional and high speed networks. Additionally, numbering plan for ATM-forum is analyzed.

To transmit multimedia information efficiently and use it in realtime, it needs a private multimedia terminal for service type. But multimedia information terminal was developped for of offered service type in case by case. Accordingly, general multimedia terminal have not been developed yet. Multimedia database structure and standard communication protocol must be designed first to develop the general multimedia terminal. Multimedia database structure needs to store the various multimedia information consistently and, standard communication protocol access the database transparently. In this paper, we design a multimedia database structure and communication protocol that are able to access the multimedia information on distributed database servers in the network.

In this paper, programmable abstractions of the underlying resources of the IP router are proposed for designing a software architecture of the next generation router, which can provide the variety of QoS services and reliable and complicate network services.

The researches about the stratospheric communication system are on process in USA, Japan, Europe and etc. The Airship is expected to be fixed at its position in stratosphere but perhaps its position is changed slightly because of wind in stratosphere. If earth station antenna has high gain without tracking function, even though the airship location has a little variation, degradation of antenna gain is occurred because of narrow beamwidth. In this paper, EIRP and G/T variation of the ground system due to the position variation of airship are examined.

This paper presents the radio propagation effects in the shadow region due to the presence of obstacle, like building and tree, along the path at the B-WLL band. Using the Uniform Theory of Diffraction(UTD), the total field was obtained as the sum of contributions with diffraction ray from the each obstacle's edge, the direct ray, and the reflected rays from ground. The normalized signal level(in ㏈) is calculated with the parameters of the base station elevation and the distance between obstacle and receiver. This results are used to provide the suitable radio cell planning and coverage prediction in the area of shadow region.

본 논문에서는 KOMPSAT에 사용할 S-band 위성중계기 (RF transponder)에 사용되는 Power Amplifier에 대한 설계와 제작에 대하여 논하고자 한다. 또한 이 설계에 대한 검증을 수행하기 위하여 impact analysis 와 기본적인 이론을 정리 한 후 모의 설계를 통해 설계 가능성을 검토하였다. 현재 당사가 개발 추진중인 다목적 실용 위성 ( KOMPSAT) 에 이용될 S-band Transponder 의 주파수는 uplink 2099.5㎒ 와 downlink 2280㎒를 근간으로 설계하였으며, 회로 시뮬레이션을 위해 사용된 software는 ADS(advanced Design System : HP) 및 ISSPICE 4 E.2 이며, Monte Carlo Analysis funtion 을 이용하여 대수학적으로 전개하였다.

In this paper, we describes RF receiver module for IMT-2000 handset with 5MHz channel bandwidth. The fabricated RF receiver module consists of Low Noise Amplifier-, RF SAW filter, Down-converter, IF SAW filter, AGC and PLL Synthesizer. The NF and IIP3 of LNA is 0.8㏈, 3㏈m at 2.14㎓, conversion gain of downconverter is l0㏈, dynamic range of AGC is 80㏈, and phase noise of PLL is -100 ㏈m, at 100KHz. The receiver sensitivity is -110㏈m, adjacent channel selectivity is -48㏈m.

In this article, as a way of pursuing high spectral efficiency and flexible cell planning, co-channel dual-polarization techniques are suggested for B-WLL applications. It provides a double down stream capacity compared with conventional scheme and also makes some flexibility in cell planning. In order to implement co-channel B-WLL system, some frequency plans, interference cancellation methods, and system block diagrams are presented here.

In this paper, we design the analog phase shifter for the elimination of the ghost signal. Compensation of the delay between the reference signal and the relatively delayed signal is possible. This phase shifter uses the vector summing method. We use for the attenuator in our system FETs. The phase shifter is operated at the 200MHz and composed by lumped elements. The proposed analog phase shifter is simulated by the HP ADS software.

KORTASAT-III is planning to provide Ka-band broadband communication service, including eastsouth Asia area. In this paper, we calculate the link budget for Ka-band KOREASAT-III multimedia service and describe the performance of multimedia services according to link design parameters. There are Trunk service, Television receive only service, Two-way point-to-multipoint service, Tele-education service in the service scenario.

In this paper, a wideband MMIC LNA was designed using low Q matching network. Gains of 9.8~12.2 ㏈, and noise figures of 1.7~2.1 ㏈ were obtained from the fabricated wideband MMIC LNA in the frequency ranges of 1.5~2.5㎓. And maximum output power of 10.83 ㏈m were obtained at the center frequency of 2 ㎓. The chip size of the fabricated wideband MMIC low noise amplifier is 1.4 mm$\times$1.4 mm.

It is difficult to analyze the impact of interference of NGSO/FSS systems on a GSO/FSS network because of time-varying nature of NGSO/FSS systems. In this paper, we present an efficient method to assess the impact of interference of NGSO/FSS satellite networks on the GSO/FSS carrier performances. The example analysis shows the impact on the GSO/FSS carrier performances in terms of elevation angles of earth stations in a GSO/FSS system.

The interference situation from NGSO/FSS network to GSO/FSS network is more complicated than the situation between GSO networks because of the time varying orbital characteristics of NGSO systems. In this paper, the interference characteristics for several types of hand-over strategies are simulated and it is shown that the results should be useful in practical coordination of inter-network interference.

We designed and fabricated partially shorted QMSAs(Quarter-Wavelength Microstrip Antennas) for 850［MHz］band on various Copper-clad Laminates substrates (TACONIC company), where the width of the radiation patch is identical with that of the ground plane and the radiation patch is partially shorted to the ground plane. The resonant frequencies and the return losses according to the electrical thickness were measured by reducing the PSW (Partially Shorted Width) to 0［mm］. As a result, a good characterized antenna with an average 11% reduced resonant length and a return loss -15.86~-30.68［㏈］ was obtained when the total PSW was in the range of 70% of radiated patch width, compared to the conventional QMSA.

A high efficient, CMOS RF power amplifier at a 2.SV power supply for the band of 902-928MHz was designed and analyzed in 0.25${\mu}{\textrm}{m}$ standard CMOS technology. The output power of designed amplifier is being digitally controlled from a minimum of 2㎽ to a maximum of 21㎽, corresponding to a dynamic range of l0㏈ power control. The frequency response of this power amplifier is centered roughly at 915MHz. The power added efficiency of designed amplifer is almost 48% at maximum output power of 21㎽.

In this paper, we present a FPCA implementation of IDEA algorithm. Target technology is Altera FLEX 10K FPCA. The correctness of the implementation is verified by the timing simulation with max+plus II.

We designed a 128-tap FIR filter for a modem which complies with ITU-T V.32. We adopted pipeline technique and realized delay-taps with two ring-buffers. The multiplier in this filter carries out 2's complement fixed-point multiplication of 14bit $\times$ 16bit. The designed filter is expected to operate at 50MHz.

In this paper, we designed a Viterbi decoder with constraint length K=7, code rate R=1/2, encoder generator polynomial (171, 133)$_{8}$. This decoder makes use of 3-bit soft decision. We designed the Viterbi decoder using VHDL. We employed conventional logic circuit instead of ROM for branch metric units(BMUs) to reduce the number of gates. We adopted fully parallel structures for add-compare-select units(ACSUs). The size of the designed decoder is about 200, 000 gates.s.

In this paper, we designed a 8-bit flash ADC, which can be used in fully differential circuits. We adopted a 2-step flash architecture with digital correction. The designed ADC is expected to work at the sampling frequency of 30MHz. We carried out the layout with 0.65${\mu}{\textrm}{m}$ CMOS technology The core size is 1.587mm$\times$1.069mm.

We propose a low complexity M-D(multidimensional) TCM decoder VLSI architecture for ADSL System. We use the shared subset decoder module by modifying the whole decoding procedure. We reduce power consumption by using the MSA (modulo set area) operation, which removes multiplication in 4D metric calculation. Also the proposed TCM decoder reduces chip area. It can be adopted in high-speed xDSL system.

In this paper, we measured and simulated the transconductance change of submicron LDD NMOSFETs due to back bias under various channel length, temperature and substrate doping conditions. As back bias is increased, the mobility will decrease and g$_{m}$ decreases according to a conventional model. But as the channel length is reduced, this phenomenon is inverted and g$_{m}$ increases in the submicron region. This can be explained by analyzing the electron quasi Fermi potential in the channel. And the empirical formulae which show the g$_{m}$ change were induced. These will be helpful to enhance the efficiency and precision of IC design.esign.

The effects of the substrate bias on the performance of programming erasing in p-channel flash memory cell have been investigated. It is found that applying positive substrate bias can improve the programming and erasing speed. This improvements can be explained by Substrate Current Induced Hot Electron Injection. From the results, we can confirm that BTB programming method is better in programming and erasing speed than CHE programming method.

We deposited tungsten gate electrode on gate SiO$_2$by thermal LPCVD with WF$_{6}$, SiH$_4$ and H$_2$. The resistivity was ~10$\mu$Ωcm and exhibited good adhesion ability on oxide when the temperature was higher than 40$0^{\circ}C$. We find that, however, both the low-field current and the charge-trapping characteristics were inferior to the control devices. The oxide degradation by fluorine during the tungsten deposition must be minimized to use the tungsten as alternative gate electrode.e.

The etch characteristics of E-ICP and ICP are compared for the improvement of SiO$_2$ etch Process. Etch rate and etch pattern profile are measured by $\alpha$ -step surface profiler and SEM, respectively. The E-ICP provides improved characteristics on etch rate and surface profile in comparison to ICP process.

ICP reactor produces high-density and high-uniformity plasma in large area, are has excellent characteristic of direction in the case of etching. Until now, many algorithms used one mesh method. These algorithms are not appropriate for sub 0.1 ${\mu}{\textrm}{m}$ device technologies which should deal with each ion. These algorithms could not present exactly straggle and interaction between projectile ions and could not consider reflection effects due to interactions among next projectile ions, reflected ions and sputtering ions, simultaneously. And difficult consider am-bipolar drift effect.

We calculated Al-Absorption, Al-reflection, and Si-etching probabilities as a function of incident angle and energy using classical molecular dynamics (MD) simulation. Variations of the cases of Al-absorption rate and Al-reflection rate are less than that of Si-etching rate. In contrast with general prediction, our simulation results showed that channeling of the <110> direction occurred the most in the case of incident angle between 30degree and 40degree. We investigated that channeling of the <110> directions quite affect Al-absorption rate in silicon. Since Si-etching rate is high and Al-absorption rate by <110> channeling is high, we found that Al ionized physical vapor deposition (PVD) on Si(001) has a different characteristics with Al ionized PVD on A1(111).

In this paper, we designed a equalizer that moved the multipath of channel in 8-VSB transmission receiver. After doing the initial equalization with "LMS(Least Mean Square)"aigorithm. this equalizer used "Stop-and-Go" algorithm. Because of estimating SER(Symbol to Error Ratio) every a training sequence, this can positively cope with transformation of channel and because of using fast clock than symbol-clock(10.76 MHz), we are able to reduce a multiplier.

In this paper, we present a polysilicon actuator on silicon wafer using surface micromachining technology which employs an electrostatic stepwise driven Scratch Drive Actuator to generate a force that can move an external object. For optical applications, we propose wavelength selector using distributed feedback structures and this micro actuator.

This paper describes realized APC and pre-equalizer circuit, and their operation principle and test results. In analog optical transmitter, constant lasing power control, free of signal clipping and linearity are important considerations. We examined pre-equalizer and APC(Automatic Power Control) circuit to improve the analog optical transmitter performance.

Recent developments of carbon nanotubes are reviewed［1,2,3,4］. We use Tersoff carbon potential for bonded interactions［5］ and Lennard-Jones 12-6 potential for non bonding interactions［6］to describe mechanical properties of the temperature-dependent armchair single wall carbon nanotube. At first we report that through defect number and bonding energy calculation, how single wall carbon nanutube is capped in the constant temperature. (300K, 2000K, 3000K, 4000K) At second, we perform MD simulation, which are performed on the energy optimized structure of carbon nanotube.

Modal transmission-line theory is described for guided electron waves in quantum-well structures. To demonstrate the validity and usefulness of this approach, we evaluate the propagation characteristics and the coupling properties of electron guiding couplers consisting of double quantum-wells (DQWs).

By controlling the pixels of a liquid crystal display (LCD) electronically, we fabricated a real-time moving window on a LCD, through which light passes. Using the moving window and hi-focusing lens, we suggested a non-mechanical spatio-angular multiplexed holographic memory system and demonstrated its feasibility through optical experiments. The principle of the proposed method and optical experimental results are also presented.

A multi-channel gas leakage monitoring system was designed and fabricated by using CPLD(complex Programmable Logic .Device) for monitoring and controlling the leakage of natural gas from supplying-pipes under the ground. Fabricated SnO$_2$thick film gas sensor elements were attached on safeguard steel plate of natural gas supplying pipes, and the local monitoring system in this study received the signal from the gas sensors. The monitoring system was implemented by using CPLD chip to reduce the development time and implement simple one chip system. The time division multi-channel system received the input signal from individual gas sensor at one of divided times by multiplexor and signal processed sequentially. The system reduced the size of peripheral circuit resulted in implementation of creditable simple system.

For applications in multimedia to which genuine RISC microprocessors are not suitably applicable, a new generation of fast and flexible microprocessors is required. In this paper, as a technique of integrating DSP functionality in a general RISC processor, a RISC that can execute DSP extension instructions is developed to improve the performance of multimedia application execution. This processor can execute DSP instructions in parallel with the execution of ALU instructions for efficient and fast execution. In addition, the execution ability of integer instructions is improved by enhancing the RISC core itself.

메모리 테스트는 Built-In Self Test(BIST)와 같이 메모리에 내장된 회로를 통하여 자체 점검하는 방법과 테스터를 통하여 생성된 패턴을 주입하는 방법이 있다. 테스트 패턴 생성방법으로는 각각의 고장모델에 대한 테스트 패턴을 deterministic하게 생성해주는 방법과 Pseudo Random Pattern Generator(PRPG)를 이용하여 생성하는 경우로 구분할 수 있다. 본 연구에서는 PRPG를 패턴 생성기로 사용하여 여러 가지 메모리의 결함을 대표한다고 볼 수 있는 Static 및 Dynamic Neighborhood Pattern Sensitive Fault(NPSF) 등 다양한 종류의 고장을 점검할 수 있도록 메모리 BIST를 구성하였다. 기존의 Linear Feedback Shift Register(LFSR)보다 본 연구에서 제안하는 Linear Hybrid Cellular Automata(LHCA)를 이용한 PRPG가 높고 안정된 고장 점검도를 나타내었다.

In this paper, Tele-Test System for ASIC Design is constructed. It consists of the server, and the clients. The server and clients are implemented by Java. Using Java RMI system, the remote access via information network is implemented. In this Tele-test system, fault simulation, test pattern compaction, test pattern generation, and path-delay fault test generation services are implemented. All service can be peformed parallel by network access.

In this paper, we present a new clock routing algorithm which minimizes total wirelength under any given path-length skew bound. The algorithm onstructs a bounded-skew tree(BST) in two steps:(ⅰ) a bottom-up phase to construct a binary tree of shortest-distance feasible regions which represent the loci of possible placements of clock entry points, and (ⅱ) a top-down phase to determine the exact locations of clock entry points. Experimental results show that our clock routing algorithm, named BST/DME, can produce a set of solutions with skew and wirelength trade-off.

The PLD design of new scheme LCD driver circuit is described in this paper. A new scheme LCD driver circuit doesn't used microprocessor for the convenience of users. A new scheme LCD driver circuit consists of 4 main parts, that is, a serial/parallel communication control block part, a LCD controller part, a LCD driver part and a RAM/ROM control block part. The validity and efficiency of the proposed LCD driver circuit have been verified by simulation and by ALTERA EPM7192SQC160-15 PLD implementation in VHDL. After comparing this LCD driver circuit to specify it was verified that the developed LCD driver circuit showed has good performances, such as low cost, convenience of users.

A direct digital frequency synthesizer is designed in full custom method using 0.65${\mu}{\textrm}{m}$ CMOS n-well technology The chip provides the capability of the parallel operation using up to 4 chips with an operation frequency of 440MHz. The generated waveform can be modulated by various modulation techniques such as QPSK, 256 . 64. 32 . 16 QAM and FM.

We designed a phase locked loop (PLL), which is applicable to microprocessor clock generation application. The designed PLL has a new simple phase frequency detector (PFD) which eliminate dead-zone and has a good high frequency characteristic. The lock-in range of the designed PLL is 50 MHz ~ 150 MHz at 3.3v power supply voltage. The design is carried out using a 0.6${\mu}{\textrm}{m}$ triple metal CMOS process. The area of the layout is 0.35mm by 0.42mm with 359 transistors.

예전에 일반적인 DC모터제어 또는 전류 량 제어 분야에만 사용되던 펄스 폭 변조기 형태의 부품이 근래에는 멀티미디어 단말장치의 한 부품으로 사용되고 있는데 본 논문에서는 비디오 신호처리 및 영상보드에서 간편하게 사용될 수 있는 PWM 모듈을 설계하였다. 단말장치의 주변 칩에서 사용되는 일반적인 내장형 모듈을 사용하게 되면, 멀티채널을 요하는 시스템에서 채널의 부족으로 인해 여러 개일 마이크로 콘트롤러를 사용해야 하는 단점이 있다. 이 때문에 내장형으로 사용될 수도 있으며, 독립적으로도 동작할 수 있는 구조가 필요하며 정적으로 동작해야 하는 시스템에도 이식될 수 있는 기능도 동시에 가지고 있어야 한다. 본 논문에서는 이러한 기능을 만족시키기 위한 진보된 PMW 모듈의 구조를 제안하였으며, 이를 VHDL로 기술하여 기능을 검증하고, XC4010XL-PC84 FPGA로 구현하였다.

This Paper describes the design of high speed and low power comparator based on the feed forward bias control. Major building blocks of this comparator are composed of input offset canceling circuit and feed forward bias control circuit. The usual offset canceling circuit cancels the offset voltages by storing them in capacitors using MOS switches, The comparator of this paper employs the bias control circuit which generates bias signal from the input signal. The bias signal is applied to the capacitors and keeps the transfer of chares in the capacitors in the minimal amount, therefore making the comparator operate in stable condition and reduce decision time. The comparator in this form has very samll area and power dissipation. Maximum sampling rate is 200 Ms/sec. The comparator is designed in 0.65${\mu}{\textrm}{m}$ technology and the offset is less than 0.5㎷.

A novel linear transconductor for low-voltage low-power signal processing is proposed. The transconductor consists of a pnp differential-pair and a npn differential-pair which are biased by local negative feedback. The simulation results show that the transcondcutor with transconductance of 50 $mutextrm{s}$ has a linearity error of 0.05% and the power dissipation is 2.44 ㎽ over an input linear range from -2V to +2V at supply voltage $\pm$3V.

A offset compensated class A bipolar second-generation current conveyor (CCII) for high-accuracy current-mode signal processing was proposed. The CCII adopts two diode-connection transistor between voltage input and voltage output to reduce offset voltage. Experiments show that the proposed CCII has offset voltage of 0.05 ㎷, input impedance of 2 Ω and the 3-㏈ cutoff frequency of 30 MHz when used a voltage amplifier. The power dissipation is 6 ㎷.

The transmission line effects of IC interconnects have a substantial effect on a hish-speed VLSI circuit performance. The effective transmission lime parameters are changed with the increase of the operation frequency because of the skin of the skin effect, proximity effect, and silicon substrate. A new signal delay estimation methodology based on the RLC-distributed circuit model is presented ［2］. The methodology is demonstrated by using SPICE simulation and a high-frequency experiment technique.

A new accurate as well as efficient multi-layer interconnect capacitance extraction method is presented. Since Multi-layer interconnects is too complicated to directly extract capacitances, it is simplified with virtual ground concept. To make the structure tractable, the shielding effects should be separately determined. Since the electric field shielding effects, and the solid-ground-based capacitance matrices can be readily determined from the layout geometry, the accurate as well as efficient quasi-3D capacitances concerned with an objective line can be readily determined. In order to demonstrate its efficiency and accuracy, the parameters and circuit responses were benchmarked with 3D-field-solver-based results.

This paper describes the architecture and the IC implementation of a Direct Digital Frequency Synthesizer (DDFS). That is based on an angle rotation algorithm (CORDIC). It is shown that the architecture can be implemented as a multipliers, feedfoward, and easily pipelineable datapath. A prototype IC has been designed, fabricated in 0.35${\mu}{\textrm}{m}$ SAMSUNG KG90 Library.

Battery로 작동되고, 소형인 제품들도 다양한 기능은 물론이고, 다양한 입출력 장치를 갖추고, 실시간으로 처리하는 시스템이 많이 요구되고 있는 실정이며, 점차 더욱 더 요구될 것으로 전망된다. 더욱이 포터블 기기는 일반적으로 MCU의 내부에 제한된 ROM type 메모리를 내장하게 되면, 데이터 메모리로 SRAM 및 flash memory를 갗추고 있다. 따라서 이러한 제한된 하드웨어 환경하에서 많은 기능을 수행해야 하는 경우가 많다. 여러 기능을 시간적인 간격으로 배분하거나, 기능 자체를 서로 배분하면서, 서로 융합하는 등의 여러 가지 기능을 수행하려다보면, 당연히 메인 소프트웨어 구조가 복잡해지며 대부분 어셈블리나 C와 같은 linear한 구조를 가지는 language로 개발되기 때문에 효과적인 프로그램 구조를 세우기는 쉽지 않다. 본 논문에서는 이를 위해 좀더 규격화된 방법을 제시하고자 한다. 보다 구체적인 구조를 연구할 목적으로 다양한 테스크를 수행하여야 하는 시스템이면서 프로세서가 필요한 포터블 기기의 한 응용 제품인 MP3 Player 에서 요구되는 job scheduling을 연구한다. 필요한 작업의 종류는 가장 부하가 많이 걸리는 압축된 MP3 file을 다시 복원시켜주는 codec 부분과 일정 시간 간격을 가지고 수행하여야 하는 외부 키보드 입력과 실시간으로 시간을 계산하는 타이머 기능, 그리고 LCD에 시간의 변화를 표시하여 주어야한다. 이와같이 수시로 작업이 발생하지만 시간 점유율이 중간 정도인 LCD 컨트롤과 메모리 컨트롤 등이다. 프로세서의 속도를 최소한으로 줄이면서 스케줄링에 의해 시간 문제를 해결하는 방법을 제시하도록 한다. 이는 기초과학 수준이 높은 북방권 국가들의 과학자들이 주로 활용되고 있다는 점에서도 잘 알 수 있으며 우리의 과학기술 약점을 보완하는 원천으로써 외국인 연구 인력이 대안이 되고 있음을 시사한다. 본 연구에서는 한국 연구 조직에서 일하는 외국인 연구자들의 동기 및 성과에 영향을 미치는 많은 요인들을 확인할 수 있었다. 상관관계, 분산분석, 회귀분석 등을 통해 활용 성과에 미치는 영향 요인들을 도출하였다. 설문 분석을 통하여 동기 및 성과 사이에는 강한 상관관계가 존재하는 것을 확인할 수 있었으며 이는 전통적인 동기 이론들과 부합한다. 대부분의 변수가 동기 및 성과에 동시에 영향을 미치는 것으로 조사되었으며 그중에서도 조직 협력 문화, 외국인 연구자의 의사소통 및 협력성, 외국인 연구자의 연구 능력 관련 변수들 및 연구 프로젝트의 기술수명주기, 외국인 연구자의 기존 기술지식의 흡수 등이 가장 중요한 변수로 나타났다. 이는 우리가 주로 중국 및 러시아 과학자들을 활용하여 상업화하는 외국인 연구인력 활용 패턴과도 일치하는 결과이다. 즉 우호적인 조직문화를 가지고 있는 연구 조직에서, 이미 과학기술 지식을 많이 가지고 있고 연구 능력도 높은 외국인 과학기술자를, 한국에서 기술이 태동 또는 성장하고 있는 연구 분야에서 활용하는 것이 가장 성과가 좋다는 사실을 확인시켜 주고 있다. 국내에서 최초로 수행된 본 연구는 외국인 연구 인력의 활용 성과가 매우 높으며, 우리의 과학기술혁신시스템을 보완하는 유효한 수단으로써 외국인 연구 인력이 중요한 대안이 될 수 있음을 발견하였다. 외국인 연구 인력을 잘 활용하기 위하여 문제점 및 개선방안을 활용 환경, 연구 인력이 중요한 대안이 될 수

본 논문에서는 휴대용 MP3플레이어에서 사용하는 파일관리프로그램에서 플래시에 데이터를 저장하고 관리하는데 따른 파일관리시스템을 설계하고 이를 구현하기 위한 기술을 논하고자 한다. 휴대용 기기에서 문제가 되는 것이 데이터의 보존을 위해 전원공급을 계속해서 해주어야 하는 문제가 가장 중요한데 이러한 제약을 극복하기 위해 전원이 공급되지 않더라고 기존의 데이터를 그대로 유지할 수 있도록 플래시메모리를 사용한다. 그러나 전원공급의 문제를 플래시로 해결했지만 플래시를 사용하는데 따른 저장공간의 제약과 데이터의 읽기 쓰기 등의 방법에서 다른 메모리와 차이가 있기에 이러한 단점을 보완해서 일반 메모리와 동일하게 사용할 수 있도록 하는 파일 관리가 필요하게 된다. 이를 위해 특정 영역을 파일정보를 담는 공간으로 할당하여 데이터 관리를 효율적으로 할 수 있도록 하고 데이터의 갱신과 저장이 용이하도록 하였다.

It is becoming increasing1y the norm for project teams to be composed of individuals who are geographically distributed but connected by high speed network. In such environments a lot of work related documents are created, so there is real needs for the system that facilitate the effective sharing, maintaining. managing of them. This paper present the system that satisfy this needs, which is known as IDOMA(Intelligent Documents management system based on Multi Agent). IDOMA is the cooperative multi agent based documents management system which has not centralized database.

Hand segmentation and tracking is essential to the development of a hand gesture recognition system. This research features segementation and tracking of hand regions based the hue component of color. We propose a method that employs HSI color model, and segments and tracks hand regions using the hue component of color alone. In order to track the segmented hand regions, we only apply Kalman filter to a region of interest represented by a rectangle region. Initial experimental results show that the system accurately segments and tracks hand regions although it only uses the hue compoent of color. The system yields near real time throghput of 8 frames per second on a Pentium II 233MHz PC.

This paper describes the recognition of totally unconstrained handwritten numerals using neural networks. Neural networks with multiple output nodes have been successfully used to classify complex handwritten numerals. The recognition system consists of the preprocessing stage to extract features using Kirsch mask and the classification stage to recognize the numerals using the fully-connected recurrent neural networks (RNN). Simulation results with the numeral database of Concordia university, Montreal, Canada, are presented. The recognition system proposed in this paper outperforms other recognition systems reported on the same database.

In this paper, a new algorithm has been presented that helps to preserve diversity as well as to enhance the convergence speed of the evolutionary programming. This algorithm is based on the cell partitioning of search region for preserving the diversity. Until now, the greater part of researches is not concerned about preserving the diversity of individuals in a population but improving convergence speed. Although these evolutions are started from multi-point search at the early phase, but at the end those search points are swarming about a one-point, the strong candidate. These evolutions vary from the original idea in some points such as multi-point search. In most case we want to find the only one point of the best solution not several points in the vicinity of that. That is why the cell partitioning of search region has been used. By restricting the search area of each individual, the diversity of individual in solution space is preserved and the convergence speed is enhanced. The efficiency of the proposed algorithm has been verified through benchmark test functions.

This paper describes a vector quantization for speech signal coding using neural networks. We processed speech signal using LPC method that extracts speech signal feature, and speech signal feature is quantized using competitive neural network kohonen self-organization feature map.

In this paper, we analysis the effect of a dictionary in a handwritten Hangul word recognition problem in terms of its size and the length of the words in it. With our experimental results, we can account for the word recognition rate depending not only on character recognition performance, but also much on the amount of the information that the dictionary contains, as well as the reduction rate of a dictionary.

In recent years, many studies have been conducted on fuzzy control since it can surpass the conventional control in several respects. In this paper, a novel approach to the stability analysis of the continuous-time affine Takagi-Sugeno fuzzy control system is proposed. The suggested analysis method is easily implemented by the recently spotlighted convex optimization techniques called Linear Matrix Inequalities (LMI).

Recently many efforts on the development of automatic processing system for delivery sequence sorting have been performed in ETRI, which requires the use of postal 4 state bar code system to encode delivery points. This paper addresses the issue on the reduction of reading error in postal 4 state raster beam based bar code reader by adjusting measured values of bar code width to its average value over each interval. The test results show that the above method reduces the average reading error rate approximately by 90-100%.

In storage technology it is desirable to have greater storage capacity at lower costs. Data compression addresses these demands by reducing the amount of data that must be stored to a given size of media, thus lowering the cost of that storage device. In data compressions it is desirable to have faster transfer rates at lower costs. Data compression addresses these demands by reducing the amounts of data that must be transferred over a media with a fixed bandwidth, thus reducing the connection the. Data compression also reduces the media bandwidth required to transfer a fixed amount of data with a fixed quality of service, thus reducing the costs on this service.

In this paper, we designed the extended ATA(AT Attachment interface with extension) interface that combines with goods price and ability and intellectual behavior of SCSI, for make progress the ability and structure of ordinary interface for connect with device of using PC. ATA is establish a standard of IDE(Intelligent Drive Electronics) public in small form factor. SCSI bus is device behaving intellectual and have stable hardware structure, calssified instructions structure. But it is device that difficult to buy, because of price of more than two times. The other side, ATA device is worse than SCSI bus in part of ability, but it came to SCSI in part of speed after improve and it's price is less expensive. another improvement of ATA is a standard of ARAP(AT Attachment Packet Interface) and use method of packet transmission and behaves as if SCSI use a method. Finally, improvement of ATAPI behave from interface of only HDD to ability of ordinary interface. This paper propose the structure of extended interface that satisfied the price and ability.

This paper propose a solution to resolve data overflow or leakage when a subscriber receive data to service provider. The set-top box can communicate with a service provider and can inform the service provider its data overflow or leakage. When service provider received this control signal, it changes data transmit rate and transmits data with changed rate. The buffer of set-top box is important because incoming data from a service provider are stored by it.

In this paper, we report on a set of new algorithms to realize a nonlinear compressed-domain video/audio editor that overcomes various realization problems. For efficiency, the underlying algorithm, which uses a central data structure in the form of doubled linked lists, performs soft edits of cut and paste (which, in turn, involves soft implementations of frame type conversion) and addresses problems relating to video/audio synchronization and random access, and decoder buffer control.

As the Internet traffic increases, the demand for higher performance routers continues to grow, and it makes switch chips more complex. To make matters worse, these chips also need to handle high-level services. In this paper, we introduce an efficient verification methodology that can support real network traffics to satisfy the verification requirement of real complex situation even at the early design phase of switch chips.

Video On Demand servers generally require massive disk storages for storing many video data. Many researches have been done on the topics of efficient allocation of movies in disks. This paper, We describe efficient disk placement techniques and implement storage system with SCSI and PCI Bus interface for efficient data handling. This paper also proposes a logical zone reconstruction method for the SCAN data placement technique. The proposed method reconstructs physical zones into logical zones by split and merge operations.

For efficient storage and retrieval of large video data sets, automatic video scene change detection is a necessary tool. Video scene changes fall into two categories, namely fast and gradual scene changes. The gradual scene change effects include, dissolves, wipes, fades, etc. Although currently existing algorithms are able to detect fast scene changes quite accurately, the detection of gradual scene changes continue to remain a difficult problem. In this paper, among various gradual scene changes, we focus on dissolves. The algorithm uses a subset of the entire video, namely the sequence of DC images, for improvement of detection velocity

UDP has likely been used for real-time applications, such as video and audio. UDP supplies minimized transmission delay by omitting the connection setup process, flow control, and retransmission In general, more than 80 percent of the WAN resources are occupied by Transmission Control Protocol(TCP) traffic as opposed to UDP's simplicity, TCP adopts a unique flow control in this paper, I report new methods to minimize a udp packet loss considering TCP flow control on the real-time application the better performance of real time application can be obtained when they reduce a packet size and FIFO buffer scheduling method competing with TCP bandwidth for the bandwidth and buffering.

Anesthesia gas to pour to patients affects the flow and volume as the pressure difference of an oxygen and an anesthesia gas. An anesthesia gas, being injurious and polluting an environment, must control the pressure of an oxygen gas because of being used by closing up tight. But a pressure sensor to use for measuring an oxygen gas appears other pressure as the characteristic and the error difference of elements to use for implementing an system. A medical machine such as an anesthesia ventilator must be accurate because of using for the person's body. So we intend to implement an system for a sensor pressure measurement not to be change regardless of an environment. This papers is the target that a sensor pressrue measurement to be changed in environment is equal to actual sensor pressure measurement. So an implemented system is using analog filter and digital filter to reduce a noise. And we are using auto-zeroing and calibration to correct a sensor pressure which is changed in environment. Through such a process we increase the accuracy and the confidence of an anesthesia ventilator by controlling the flow of an anesthesia gas.

In this paper, we studied a computer based three dimensional implantation system of artificial hip joint. The system can be utilized for doctors to select a suitable artificial femur which is best-fit for the patient and to find out the optimal implanting position as well. We proposed a new numerical index to measure the fitness between the artificial hip joint and the patient's femur. The proposed fitness index accounts for the variance of the distance between the outer contours of artificial hip joint and the femur in addition to the conventional area comparison. A few simulation are run to show results of fitness measurement and compared to the conventional method.

In this study, a new algorithm for canceling MRI artifacts through the translational motion of image plane is presented. Bloating is often makes problems in a clinical diagnosis. Assuming that the head moves up and down due to breathing, rigid translational motions in only y(phase encoding axis) direction is treated. First, we notice that the x directional motion corresponds to a shift of the x directional spectrum of the MRI signal, and the non zero area of the spectrum just corresponds to x axis projected area of the density function. So the motion is estimated by tracing the edges of the spectrum, and the x directional motion is canceled by shifting the spectrum in inverse direction. Next, the y directional motion is canceled using a new constraint, with which the motion component and the true image component can be separated. Finally, the effectiveness of this algorithm is shown by using a phantom with simulated motions.

This paper proposes a method of extracting automobile license plate information using color image processing and separation of character regions. The hue and saturation of color information is need for license plate extraction and the specified standard location ratio is need for character region separation. Simulation results show that the proposed algorithm can detect license plates and separate character regions successfully.

This paper presents a method for soccer scene analysis and coordinate transformation from scene to ground model using a priori knowledge. First, the ground and spectator regions are separated, and various objects are extracted from the separated ground region. Second, an affine model is used for mapping the object positions on the soccer image into the position on the ground model. Problems regarding holes arising from mapping processing are solved using inverse mapping instead of a usual interpolation method. Experiments are performed on a PC using about 100 RGB images acquired at 240＊640 resolution and 3∼5 frames per second.

Applications using 3D models are increasing recently. Since 3D polygonal models are structured by a triangular mesh, the coding of polygonal models in strips of triangles is an efficient way of representing the data. These strips may be very long, and may take a long time to render or transmit. If the triangle strips are partitioned, it may be possible to perform more efficient data transmission in an error-prone environment and to display the 3D model progressively. In this paper, we devised the Component Based Data Partitioning (CODAP) which is based on Topological Surgery (TS). In order to support the error resilience and the progressively build-up rendering, we partition the connectivity, geometry, and properties of a 3D polygonal model. Each partitioned component is independently encoded and resynchronization between partitioned components is done.

In this paper, video image segmentation algorithm based on color histogram and change detector is proposed. Color histograms are calculated from both changed region which is detected in the previous and current frame and unchanged region. With each histogram, modes and valleys are detected. Then, color vectors are calculated by averaging pixels in modes. Markers are extracted by labeling color vectors that represent modes, the watershed algorithm is applied to determine uncertain region. In growing region, the root mean square(RMS) of the distance between average pixel in marker region and adjacent pixel is used as a measure. The proposed algorithm based on color histogram and change detector segments video image fastly and effectively. And simulation results show that the proposed method determines the exact boundary between background and foreground.

Due to the significant computation of full search in motion estimation, extensive research in fast motion estimation algorithms has been carried out. However, most of the algorithms have the degradation in predicted images compared with the full search algorithm. To reduce an amount of significant computation while keeping the same prediction quality of the full search, we propose a fast block-matching algorithm based on gradient magnitude of reference block without any degradation of predicted image. By using Taylor series expansion, we show that the block matching errors between reference block and candidate block are proportional to the gradient magnitude of matching block. With the derived result, we propose fast full search algorithm with adaptively determined scan direction in the block matching. Experimentally, our proposed algorithm is very efficient in terms of computational speedup and has the smallest computation among all the conventional full search algorithms. Therefore, our algorithm is useful in VLSI implementation of video encoder requiring real-time application.

This paper performed a comparative study on contour tracing based thinning algorithms. These algorithms are widely used for extracting skeleton due to its superiority to other techniques in processing speed to perform comparison. We selected general eight images consisted of fingerprints, characters, and figures. According to experimental results, we compared each algorithm in performance and ability made skeleton.

In this paper, we propose a new addressing mode, which can be used for programmable image processor to perform image- processing algorithms effectively. Conventional addressing modes are suitable for one-dimensional data processing such as voice, but the proposed addressing mode consider two-dimensional characteristics of image data. The proposed instruction for two-dimensional addressing requires two operands to specify a pixel and doesn't require any change of memory architecture. Combining several instructions to load a pixel-data from an external memory to a register, the proposed instruction reduces code size so that satisfy hish performance and low power requirements of image processor. In addition, it uses inherent two-dimensional characteristics of image data and offers user-friendly instruction to assembler programmer.

본 논문에서는 영상확대 chip의 video 입력부에 부분화면을 저장할 frame memory의 구조를 개선하고자 하였다. 영상확대 video scaler인 gm833×2는 입력단 측에 frame buffer memory가 필요하게 되지만, 이를 외부에 장착하려면 일반적으로 대용량의 FIFO 메모리를 사용하게 된다. 이것은 dualport SRAM으로 구성이 되며, 메모리 제어를 고가의 FIFO칩에 의존하는 결과를 가져온다. 또한 기존의 scaler chip은 단순히 확대처리만을 하며, 입력 전, 후에 data의 변경 또는 이미지처리가 불가능한 구조가 된다. 본 논문에서는 외부에 필요한 메모리를 내장한 새로운 기능의 chip을 설계하는 데에 있어 필수적인 메모리제어 로직을 제안하고자 한다. 여기서는 더 나은 기능의 향상된 메모리 제어회로를 제시하고 이를 One-chip에 집적할 수 있도록 하였다 이를 사용한 Video Scaler Processor chip은 SDRAM을 별도의 제어회로 없이 외부에 장착할 수 있도록 하여 scaler의 기능을 향상시키면서 전체 시스템의 구조를 간단히 할 수 있을 것으로 기대된다. 본 논문에서는 먼저 메모리 제어회로를 포함한 Video Scaler Processor chip의 메모리제어 하드웨어의 구조를 제시하고, 메모리 access model과 제어로직을 소개하고자 한다.

In this papers, we proposes a efficient compression method of an image using the extraction of boundary region of DCT in MPEG-1. DCT coefficients have from low frequency to high frequency various components. After performing DCT to an image, the data is compressed to contain the boundary Region by quantization, and the information of boundary Region can be extracted by inverse DCT. In those, I chose frequency components susceptible to the boundary through the many experiences. In this paper, boundary can be selected by dividing low frequency by big quantization coefficient and dividing high frequency by small quantization coefficient without degrading visual qualify in MPEG-1. Also it is predicted that to reduce high frequency value will be good in noisy environments.

The main purpose of padding methods is to extend the boundary segments of arbitrarily shaped objects to a regular grid so that the common block based coding technique, such as 8${\times}$8 DCT, can be applied. In the conventional padding methods used in MPEG-4: LPE and zero padding, the main process is based on 8${\times}$8 blocks. On the contrary, we propose a new padding method based on pixel-by-pixel. The proposed method puts pixels into a multi-busier using the typical value of each boundary blocks and reproduces new boundary blocks. Simulation results show that the proposed method reduces the conventional padding method and improves the coding efficiency of the conventional padding method.

In this paper, we propose a real-time implementation of the MPEG-1 layer III and MPEG-2 layer III LSF audio decoding system based on OAK DSP Core. In order to solve the problem of resolution, the system has been used floating-point operation and double precision in dequantization module. The size of ROM is reduced by using the Run-length algorithm of reordered index. The subband synthesis filter module is optimized to have low computational complexity in terms of the size of ROM or RAM. To construct a efficient system, we used both the DSP Core and Parser-Huffman decoder which is implemented with VHDL.

In this paper, using one method of Additive Synthesis, Analysis-by-synthesis/Overlap-Add (ABS/OLA) method, analysis and synthesis of musical tones is processed. But peak detection of frequency domain is processed by proposed method considering the view of acoustics. It is that that harmonics frequency is times of main frequency. Using this fact, peak detection of frequency domain is useful for detection of tonal component identified musical note. It is possible to realize high-quality lour bit rate audio.

In general CELP type vocoders provide good speech quality around 4.8kbps. Among them, G.723.1 developed for Internet Phone and videoconferencing includes two vocoders, 5.3kbps ACELP and 6.3kbps MO-MLQ. Since 6.3kbps MP-MLQ requires large amount of computation for fixed codebook search, it is difficult to realize real time processing. In order to improve the problem this paper proposes the new method that reduces the processing time up to about 50% of codebook search time. We first decide the grid bit, then search the codebook. Grid bit is selected by comparison between synthetic speech, which is synthesized with only odd or even pulses of target vector. and DC removed original speech. As a result, we reduced the total processing time of G.723.1 MP-MLQ up to about 26.08%. In objective quality test 11.19㏈ of segSNR was obtained, and in subjective quality test there was almost no speech degradation.

In this paper, The Split Model Analysis Algorithm, which can generate the wideband speech signal from the spectral information of narrowband signal, is developed. The Split Model Analysis Algorithm deals with the separation of the 10$\^$th/ order LPC model into five cascade-connected 2$\^$nd/ order model. The use of the less complex 2$\^$nd/ order models allows for the exclusion of the complicated nonlinear relationships between model parameters and all the poles of the LPC model. The relationships between the model parameters and its corresponding analog poles is proved and applied to each 2$\^$nd/ order model. The wideband speech signal is obtained by changing only the sampling rate.

This note addresses the problem of reliable (equation omitted) output-feedback control design for linear systems with actuator and/or sensor failures. An output feedback control design is proposed which stabilizes the plant and guarantees an (equation omitted)-norm bound on at-tenuation of augmented disturbances including all admissible actuator/sensor failures. Based on the linear matrix inequality (LMI) approach, the output- feedback controller design method is constructed by formulating to LMIs that cover all failure cases. Ef-fectiveness of this controller is validated via a numerical example.

In this paper we developed the communication protocol in which can transmitter receive a data and instruction in pressure and control computer. This system can dramatically increase production by maximize by control the error in central unit and monitoring. When developed these pressure automatic control system, it can be automation product in factory and decrease man-power.

In this paper we analyzed each region of specific points and ｅ-Δｅphase plane in order to make fuzzy rule base. After we composed the fuzzy control rules which can decrease rise time, delay time, maximum overshoot than basic fuzzy control rules. The composed method are converged more rapidly than single rule base in convergence region. Proposed method is alternately use at specific points of ｅ-Δｅphase plane with two fuzzy control rules, that is one control rule occruing the steady state error used in transient region and another fuzzy control rule use to decrease the steady state error and rapidly converge at the convergence region. Two fuzzy control rules in the ｅ-Δｅ phase plane decide the change time according to response characteristics of plants. As the results of simulation through the second order plant and the delay time plan, Proposed dual fuzzy control rules get the good response compare with the basic fuzzy control rule.

In this paper, we consider the optimal control of detection threshold to minimize the conditional mean-square state estimation error for the probabilistic data association (PDA) filter. Earlier works on this problem involved the cumbersome graphical optimization algorithm or time-consuming numerical optimization algorithm. Using the numerical approximation of information reduction factor, we obtained the closed-form optimal detection threshold. This results are very useful for real-time implemenation.

The ECG signal is very important information for diagnosis of patient and a cardiac disorder. It is hard to remove the noise because that is mixed with a lot of noise, and the error of the filtering will distort the ECG signal. The existing method for the filtering of the ECG signal has structure that has many steps for filtering, so that structure is complex and the processing speed is slow. For the improvement of that problem, we propose the method of filtering that has simple structure using the RBF neural networks and have good results.

In this paper, A CMOS power amplifier for PCS is designed with 0.65-$\mu\textrm{m}$ CMOS technology. Differential cascode structure is used which has good reverse isolation and wide voltage swing. This amplifier circuits consist of three stages which are power amplification stage, driver stage and power control stage. We obtain output power of 30 ㏈m, IMD3 of -31㏈c and efficiency of 30 % at input power of 4 ㏈m.

We consider a negative unity feedback control system in which a controller and a given minimum phase transfer function are in cascade. This paper present a sufficient condition for the existence of a constant gain controller under which the overall closed loop characteristic polynomial is stable. This sufficient condition is based on Lehnigk's lemmas.