In this paper, ‘gesture’ is discussed as a means of human-friendly communication between man and machine. We classify various gestures into two Categories: ‘contact based’ and ‘non-contact based’ Each method is reviewed and some real applications are introduced. Also, key design issues of the method are addressed and some contributions of soft-computing techniques, such as fuzzy logic, artificial neural networks (ANN), rough set theory and evolutionary computation, are discussed.

Fast block motion estimation technique is proposed to reduce the computational complexity in video coding. In the conventional methods the size of search region is fixed. For small motion regions like background the small size of sea of search region is enough to find a block motion. But for active motion regions the large size of search region is preferred to figure out the accurate motion vector. Therefore, it is reasonable that a block motion is estimated in the variable search region (both the size and the position of it). That is to say, the search region varies according to the predicted motion characteristics of a block. The block motion in video frames has temporal continuity and then the search region of a current block is predicted using the block motion of previous blocks. The computational complexity of the proposed technique is significantly reduced with a good picture quality compared to the conventional methods.

In this paper, we propose a fast and practical head pose estimation scheme fur eye-head controlled human computer interface with non-constrained background. The method we propose uses complete graph matching from thresholded images and the two blocks showing the greatest similarity are selected as eyes, we also locate mouth and nostrils in turn using the eye location information and size information. The average computing time of the image(360*240) is within 0.2(sec) and we employ template matching method using angles between facial features for head pose estimation. It has been tested on several sequential facial images with different illuminating conditions and varied head poses, It returned quite a satisfactory performance in both speed and accuracy.

In this study, we improve the performance of a speech recognition system of visual information depending on lip movements. This paper focuses on the robustness of the word recognition system with the rotation, transition and scaling of the lip images. The different methods of lipreading have been used to estimate the stability of recognition performance. Especially, we work out the special system of the log-polar mapping, which is called Mellin transform with quasi RTS-invariant and related approaches to machine vision. The results of word recognition are reported with HMM (Hidden Markov Model) recognition system.

In this paper, we propose a watermarking method for still images using Discrete Cosine Transform (DCT). Watermarking is a copyright protection technique for digital contents by hiding secret information into the contents. The proposed method embeds the watermark information into DCT coefficients. To obtain a watermarked image that is not only high quality but also has robustness for compression, we considered a method to change the degree of embedding by utilizing the activity of each DCT block. The simulation results show that the proposed scheme can obtain huh quality watermarked images and we can extract most of the embedded data even if they are compressed by JPEG scheme.

An improved inverse perspective mapping (IIPM) is proposed so as to reduce computational expense of recovery of 3D road surface. An experimental system based on IIPM is developed to detect lane parameters for a driver assistant system. A re-organized image is obtained quickly and exactly by IIPM. Efficient preprocessing techniques are used to enhance the information of lane and obstacles. Lane in the preprocessed. image is located with region identification. Lane parameters are estimated effectively. An algorithm to adaptively modify the parameters of IIPM is given. Properties of obstacle on 3D road surface are discussed and used to detect obstacles in the current lane and neighboring lanes. Experimental results show that the new method can extract lane state information effectively.

In this paper, we propose a new dynamic bandwidth allocation and call admission control method for the VBR video sources with QoS constraints to provide user's quality of service requirements and at the same time to achieve an efficient resource management in networks. The proposed mechanism dynamically adjusts the necessary bandwidth by the networks based on the provided quality of service satisfaction degree of each connection in respect to the user's requirements in terms of loss ratio and average delay Simulation results show that our proposed dynamic method is able to provide the desired level of quality of service and high utilization.

This paper proposes a reconstruction scheme for overlapping characters in Thai printed document. Overlapping characters are characters that overlap with surrounding characters. The problem of overlapping characters is still an unsolved problem In commercially available software of Thai character recognition systems. The algorithm of reconstruction scheme is based on structural analysis of overlapping Thai printed characters. It consists of 2 steps: overlapping point determination and reconstruction of segmented characters. The overlapping point is defined as the intersection point between characters and can be determined by using templates. Then, an overlapping character is separated into segments at the intersection point. The structure of each segment may be an incomplete character and is not identical to the original one. Therefore, the reconstruction process is employed to add the incomplete part of these segments. The proposed scheme has been implemented and tested with 70 patterns of conventionally found in overlapping printed Thai characters with different typefaces and type sizes. The experimental results show that the proposed scheme can segment and reconstruct overlapping characters correctly. The proposed scheme can improve the recognition rate of commercially available software, ThaiOCR1.5 and ArnThai1.0, more than 60 percents

Low bit rate image/video coding is essential for many visual communication applications. When bit rates become low, most compression algorithms yield visually blocking artifacts that highly degrade the perceptual quality, and post-processing approaches provide one attractive solution. In this paper, we provide simple and very efficient blocking artifacts reduction method using constrained random value addition. Our method is simple enough to be used for real-time post-processing of video.

In our study, by observing and analyzing normal liver in abdominal CT image, we estimated gray value range and generated binary image. In the binary image, we achieved the number of hole which is located between pixels. Depending on the ratio, we processed the input image to 4 kinds of mesh images to remove the noise part that has the different ratio. With the Union image of 4 kinds of mesh images, we generated the template representing general outline of liver and subtracted from the binary image so the we can represent the organ boundary to be minute. With results of proposed method, processing time is reduced compared with existing method and we compared the result image to manual image of medical specialists.

For motion estimation, the block matching algorithm is widely used to improve the compression ratio of low bit-rate motion video. As a newly developed fast search algorithm, the nearest-neighbors search technique has a drawback of degrading video quality while providing fisher speed in search process. In this paper, a modified nearest-neighbors search algorithm is proposed in which a double rectangular shaped search-candidate area is used to improve video quality in encoding process with a small increasing of search time. To evaluate the proposed algorithm. other methods based on the nearest-neighbors search algorithm are investigated.

An iterative deblocking algorithm for DCT-compressed images using two-dimensional FIR filters adapted for local directionality of each block, is proposed. First, we introduce a set of simple lowpass filters, which are adapted for edges of different angles. In conventional deblocking methods based on lowpass-filtering and convex projections, a single filter is applied to a whole image. In the proposed method, on the other hand, a suitable filter is chosen out of the directional filters designed previously in every subimage (typically $8{\times}8$ block). Experimental results indicate that adaptive filtering improves PSNR at each iteration.

It is effectively removed noise in the image using FCNN(Fuzzy Cellular Neural Network) applying fuzzy theory to CNN(Cellular Neural Network) structure and HD(Hausdorff Distance) commonly used measures for object matching. HD calculates the distance between two point set of pixels in two-dimensional binary images without establishing correspondence. Also, this method is proposed in order to improve the operation speed. In this paper, $\alpha$-LTSHD(Least Trimmed Square HD) operator applying $\alpha$-Trimmed to LTSHD, one field of HD, is applied to FCNN structure, and it is proposed as the modified method in order to remove noise in the image. Also, it is made a comparison with the other filters by using MSE and SNR after removing noise using the FCNNS which are applied $\alpha$-LTSHD operator through the computer simulation. In a result, FCNN performance which is applied the proposed $\alpha$-LTSHD demonstrated the superiority to the other filters in the noise removal.

In vector quantization (VQ), mean squared difference (MSD) is a widely used distance measure between vectors. But the distance between the means of each vector elements appears as a dominant quantity in MSD. In the case of image vectors, the coincidence of edge patterns is also important when the human visual system (HVS) is considered. Therefore, we propose a new distance measure that uses the variance of differences to encode vectors and to design codebooks. It can choose more proper codewords to reduce edge degradations and make a useful codebook, which has lots of various edge codewords in place of redundant shades.

In this paper, we describe an effective method to enhance the color night images with spatio-temporal multi-scale retinex focused to the Intelligent Transportation System (ITS) applications such as in the single CCD based Electronic Toll Collection System (ETCS). The basic spatial retinex is known to provide color constancy while effectively removing local shades. However, it is relatively ineffective in night vision enhancement. Our proposed method, STMSR, exploits the iterative time averaging of image sequences to suppress the noise in consideration of the moving vehicles in image frame. In the STMSR method, the spatial term makes the dark images distinguishable and preserves the color information day and night while the temporal term reduces the noise effect for sharper and clearer reconstruction of the contents in each image frame. We show through representative simulations that incorporating both terms in the modeling produces the output sequential images visually more pleasing than the original dim images.

In this paper we propose skewed angle detection methods for images that contain text that is not aligned horizontally. In most images text areas are aligned along the horizontal axis, however there are many occasions when the text may be at a skewed angle (denoted by 0 < ${\theta}\;{\leq}\;{\pi}$). In the work described, we adapt the Hough transform, Shadow and Threshold Projection methods to detect the skewed angle of text in an input image using the orthogonal angle view property. The results of this method are a primary text skewed angle, which allows us to rotate the original input image into an image with horizontally aligned text. This utilizes document image processing prior to the recognition stage.

In this paper, we propose a progressive transmission of a video using a 2$\times$2$\times$2 DCT First of all, the video data is transformed into multiresolution represented video data using a 2$\times$2$\times$2 DCT. Then. it is represented by a 3-D EZT(Embedded Zero Tree) coding fur the progressive transmission with a bit-rate scalability. The proposed progressive transmission algorithm needs much less computations and buffer memories than the higher-order convolution based wavelet filter. Also, since the 2$\times$2$\times$2 DCT requires independent local computations, parallel processing can be applied.

In the basic continuous ARQ schemes (Go-Back-N or Selective Repeat ARQ), each block is continuously transmitted without interruptions. Only when the transmitter receives NAK from the receiver side, the transmitter stops sending current data block and retransmit the erroneous block (Naked block). When channel error rate increases and become sufficiently high, there exists a point at which each block of message is transmitted, on average, more than once. Under such conditions, it will be more efficient to send continuously two or more copies(generally $\ell$ copies) of each block from the first transmission over noisy channel. A request for repeat will be made again only when none of $\ell$ duplicates are received correctly. By this way, the proposed scheme yields a better throughput efficiency and holds nearly constant throughput as compared to others continuous A.R.Q schemes under wide error rate variations (0 < P < 0.3).

Industrial communication networks have attracted much attention in the area of decentralized control systems for factory automation and computer integrated manufacturing. In this paper, we investigate the rate-based traffic control of industrial communication networks employing LonWorks to improve the performance measures of throughput, fairness, and error rates. To this end, we utilize the Feedback channel information through the additional network monitoring node and make the overall system closed-loop. We demonstrate the improved performance of the controlled network system by the experimentation upon an implemented lab-scale network system.

Decision-makers in ecological system and social system have complex interactions and relations. Such interactions and relations are not predefined but dynamically constructed. We consider what relation-s are constructed or destroyed and how the relations change. Therefore, we focus on the formation and collapse of relations as one of the emergent phenomena of social or ecological complex phenomena. Game theory is the best way of analyzing phenomena in terms of interactions. However, it is difficult to analyze the dynamical system by game theory. Consequently, we propose Selecting Game with agents as players based on game theory. In this model, the relations among agents are not predefined but constructed by selecting subgames. As a result, we confirmed that the entire relation among agents is constructed by the agents＇ changing partial relations and that the relations dynamically change.

The system has a function of acquirement PCM signal of the preferred channel from the subhighway (SHW), connecting a universal signal transceiver unit and time switch unit, and then it classifies the type of signal such as R2MFC/ DTMF/ CCT/ VOICE, and finally discriminates the digit. This paper describes the spectral analysis of the PCM acquisition system usng the quick Fourier transform(QFT), and discusses the algorithm of signal analysis and discrimination.

In this paper we approach the problem of congestion control for TCP traffic over ATM-UBR networks by focusing on the fact that to get best performance. We study how to efficiently support TCP traffic in the subnet ATM model, when ATM is only a single link in the whole path. We show that when UBR connection. We analyze the ATM-UBR network service using the BSD 4.3 Reno, Tahoe TCP. However we found the fact that the characteristic of fast recovery algorithm makes a serious degradation of performance in multiple cell loss drop situation. We propose new fast recovery algorithm to solve the problem.

In this paper, we propose a call admission control(CAC) scheme fer the mixed voice/data DS-CDMA systems and analyze the Er-lang capacity under the proposed CAC scheme. Voice and data traffics require different system resources based oil their Quality of Service(QoS) requirements. In the proposed CAC scheme, some system resources are reserved exclusively for handoff calls to have high priority Over new calls. Additionally the queueing of both new and handoff data traffics that are not sensitive to delay is allowed. Ar a performance measure for the suggested CAC scheme. Erlang capacity is utilized. For the performance analysis, a four-dimensional Markov chain model is developed. Erlang capacity of a practical IS-95B type system depicts, and optimum values of system parameters such as the number of reservation channels and queue lengths are found with respect to Erlang capacity. Finally, it is observed that Erlang capacity is improved more than two times by properly selecting the system parameters with the proposed CAC scheme.

In previous research of social dilemma, there is no extended game that the players can select one game out of some social dilemma games. We propose this kind of game as ＂Distributed Social Dilemma＂ In this game, each player tries to acquire the adaptive strategy throughout local interactions. We make use of GA as evolutionary operations. In this paper, our purpose is to examine how the game selection of players influences the evolution of cooperation in distributed social dilemma. In order to examine, we formulate distributed social dilemma by Game Theory and use agent-based simulation that each agent is regard as player

Nowadays, the issue of congestion control in high-speed communication networks becomes critical in view of the bandwidth-delay products for efficient data flow. In particular, the fact that the congestion is often accompanied by the data flow from the high-speed link to low-speed link is important with respect to the stability of closed-loop congestion control. The Virtual-Connection Network (VCN) in Gigabit Ethernet networks is a packet-switching based network capable of implementing cell- based connection, link-by-link flow-controlled connection, and single- or multi-destination virtual connections. VCN described herein differ from the virtual channel in ATM literature in that VCN have link-by-link flow control and can be of multi-destination. VCNs support both connection-oriented and connectionless data link layer traffic. Therefore, the worst collision scenario in Ethernet CSMA/CD with virtual collision brings about end-to-end delay. Gigabit Ethernet networks based on CSMA/CD results in non-deterministic behavior because its media access rules are based on random probability. Hence, it is difficult to obtain any sound mathematical formulation for congestion control without employing random processes or fluid-flow models. In this paper, an analytical method for the design of a congestion control scheme is proposed based on Smith＇s principle to overcome instability accompanied with the increase of end-to-end delays as well as to avoid cell losses. To this end, mathematical analysis is provided such that the proposed control scheme guarantees the performance improvement with respect to bandwidth and latency for selected network links with different propagation delays. In addition, guaranteed bandwidth is to be implemented by allowing individual stations to burst several frames at a time without intervening round-trip idle time.

The economical detection of dual-tone multifrequency(DTMF) signals is an important factor when developing cost-effective telecommunication equipment. Each channel has independently a DTMF receiver, and I t informs the detected signal to processors. This paper analyze the power spectra and evaluate the performance of DTMF receiver by using tile quick Fourier transform(QFT) algorithm. As experimental results, it show the improved performance to the DTMF receivers and reduce memory waste and process the real-time.

In this paper, performance of multicode DS/CDMA packet radio network with adaptive antenna array is analyzed and simulated in a multipath Rayleigh fading channel. The network performance is evaluated in terms of packet throughput. From the simulation results, it is confirmed that the adaptive antenna array is very effective in improving the packet throughput performance of the multicode DS/CDMA packet radio network. The results of this paper can be applied to design of IMT-2000 or future-generation mobile communication systems.

Phase noise of oscillator gives the performance degradation significantly when a high carrier frequency and low transmission rate are used. The BER(Bit Error Rates) degradation of QPSK(Quadrature Phase Shift Keying) transmission is analyzed with the oscillator phase noise level specified in downstream physical interface of LMDS(Local Multipoint Distribution Services) which is described in DAVIC(Digital Audio Visual Council). The model used for the phase noise is a power-law model. We also investigated the effects of the various transmission rates on system performance. For the transmission rate below 0.5 Mbps, the BER performance is severely degraded and we verified that the transmission rate, 20 Mbps, is adequate for the downstream of LMDS systems.

As the use of real-time multimedia applications increases, a considerable amount of “greedy” UDP traffic would easily dominate network bandwidth and packet loss. As a result, bandwidth available to TCP connections is oppressed and their performance extremely deteriorates. In or-der that both TCP and UDP sessions fairly co-exist in the Internet, it is vital that we consider the fairness among both protocols. In this work, we implement a “TCP-friendly” rate control mechanism suitable to video applications and con-sider its applicability to a real system through observation of the video quality at the receiver and the connection state. It is shown that we can achieve high-quality and stable video transfer fairly sharing the network bandwidth with TCP by applying our rate control at a control interval of 32 times as long as RTT.

In this paper, we evaluate the interference statistics between the competiting wideband CDMA systems, and optimize the frequency coordination between Wideband-CDMA systems by the Monte-Carlo methodology. We develop the simulator to analyze the radio interference between CDMA systems. It can calculate or estimate the probability of interference from adjacent frequency band, which is also power controlled. We simulate the interference effects between two Wideband CDMA systems. We present the required carrier distance and zone for two operators to meet the required coverage efficiency and outage probability of Signal to interference plus noise ration (SINR).

In this paper, we derive forward link Erlang capacity reflecting both outage probability and blocking probability of each traffic type in mixed traffics environment. We firstly determine the number of available virtual trunks of the forward link from a circuit switching perspective. Then, capacity sharing model and generalized Erlang model are employed to derive joint Erlang capacity of various traffics types.

A new analog synchronous mirror delay to be used in the wide-bandwidth clocking circuits is proposed to overcome the frequency dependency of the negative-delay values in the conventional analog synchronous mirror delay. The scheme adopts a new dummy-delay compensation technique by adopting the comparator with inherent systematic offset to achieve the enhanced negative-delay range especially prominent at high frequency applications.

In this paper, we propose to exploit a multi-code CDMA scheme for power line communication (PLC) systems, and its performance on non-Gaussian impulse and harmonic noises is presented. The proposed multi-code CDMA scheme utilizes convolutional coding and block interleaving to combat with the non-Gaussian noises, and simulation results indicate effective alleviation of these noises, and thus significant bit error rate improvement by the proposed scheme even under strict restriction of frequency band allowed in PLC systems.

In this paper, we use U-Mart that is an agent-based artificial market model. U-Mart is more open than the other artificial market, because In U-Mart, not only computer program agents, but also human agents are able to participate in the market. Therefore, the market in U-Mart gets closer to the real markets and the agents that participate in the market make the complex decision. Moreover we expand to the number of brand to plural. This expansion causes to appear the several strategies to make a profit. As one of this example, we treat the portfolio and confirm the possibility of getting the constancy to make portfolio.

In this paper, forward error control coding in multicarrier direct sequence code division multiple access (DS/CDMA) systems is considered. In order to accommodate a number of coding rates easily and make the encoder and do-coder structure simple, we use the rate compatible punctured convolutional (RCPC) code. We obtain data throughputs at several coding rates and choose the coding rate which has the highest data throughput in the SINR sense. To achieve maximum data throughput, a rate adaptive system using channel state information (the SINR estimate) is proposed. The SINR estimate is obtain by the soft decision Viterbi decoding metric. We show that the proposed rate adaptive convolutionally coded multicarrier DS/CDMA system can enhance spectral efficiency and provide frequency diversity.

In this paper, we propose two receiver structures of the impulse radio (IR) system to improve its performance in multipath environments. Recently, the impulse radio system has drawn much attention for future high-speed wire-less communication services. The conventional IR receiver directly correlates received signals with the ideal reference waveform, which results in performance degradation in multipath environments. The Key idea of the proposed receiver structures is to reflect the multipath Characteristics into the IR receiver. One is to deconvolve the received waveform with estimates of the multipath gains to obtain the transmitted waveform while the other is to modify the reference waveform of the correlator according to the estimates of the multipath gains. We examine the performance of the proposed schemes for the statistical indoor wireless communication channel model using computer simulation.

This paper proposes a novel circuit configuration realizing biquadratic voltage transfer functions using three CCIIs and six passive elements. The circuits realize high-pass, band-pass, low-pass, band-stop and all-pass functions by selecting input voltages. The circuit has low passive sensitivities and permits orthogonal adjustment of quality factor Q and cutoff angular frequency $\omega$$\sub$o/. The effects of non-ideal CCIIs on biquadratic transfer functions are also given.

Circuit configurations for realizing of biquadratic current transfer functions using current conveyors (CCIIs) are presented. The circuits are composed of three multiple-output CCIIs and four passive elements (two resistors and two grounded capacitors), and when current controlled conveyors (CCIIs) in place of CCIIs are employed, the circuit can be realized using three multiple-output CCIIs and two grounded capacitors. Use of grounded capacitors is suitable for integrated implementation. The cutoff frequency of a realized filter with current gain K can be tuned independently of Q by the value of K.

Novel simulated floating inductor (SFI) using fully-differential operational transconductance amplifier (FOTA) is presented. The SFI only consists of two FOTA and a capacitor. A ladder-type third-order elliptic low-pass filter is also presented for the SFI’s application. The theory of operations described and the simulation results are used to verify theoretical predictions. The SFI shows close agreement between predicted behavior and simulation performance. The simulation results that the SFI have The temperature coefficient of-179 ppm/$^{\circ}C$ and Q factor of 120 at 200kHz at supply voltage ${\pm}$5 V.

The design, numerical simulation, and an experimental implementation of two-element cross-shaped microstrip line-fed printed slot array antenna for IMT-2000 at the 2.0 GHz band is presented in this paper. The proposed antenna with relative permittivity 4.3 and thickness 1.0mm is analyzed by the Finite-Difference Time-Domain (FDTD) method. It was shown that the measured 2.0 VSWR bandwidth of one-element microstrip slot antenna is from 1.42 GHz to 2.69 GHz, which is approximately 61.8% and that of two-element microstrip slot array antenna is from 1.42 GHz to 2.56 GHz, which is approximately 57.3% And it was shown that the measured gain of one-element microstrip slot antenna is 2.75 dBi and that of two-element microstrip slot antenna is 4.75 dEi. The antennas were fabricated and tested. The measured results are in good agreements with the FDTD results.

This paper describes a novel multi-operand radix-2 signed-digit(SD) adder. The novel multi-operand addition algorithm can eliminate carry propagation chain by dividing the input operands into even place part and odd place part, and adding them each. The multi-operand adder with this algorithm can add six operands in parallel, and is faster than the ordinary method of SD adder binary tree. A hardware model for proposed adder is shown which is implemented by the current-mode MOSFET circuit technology. Simulations have been made by SPICE in order to verify the function of the proposed circuit.

This paper proposes a pipelined adaptive filter based on affine projection algorithm with order 2. This filter gives a better convergence performance than that of LMS or NLMS pipeline algorithm and has same latency with the pipeline algorithm based on equivalent transformation. Compared to the critical path of the pipeline NLMS implementation, only 2 additions are increased in that of the proposed implementation.

The resonance characteristic of microstrip antenna with an airgap between the substrate layer and ground plane is investigated. The study is performed by using a rigorous Green’s function formulation in the spectral domain and Galerkin’s moment method calculation. The numerical convergence using sinusoidal basis functions, the unknown surface current distribution in the rectangular patch, is discussed. Numerical result for the effects of airgap and patch length on the complex resonant frequencies of the rectangular microstrip structure are also presented

Adiabatic dynamic CMOS logic circuits, which are called ADCL circuits, promise us to implement low power logic circuits. Since the power supply source for ADCL circuits had not been developed, we proposed a power supply circuit for them. It is shown experimentally that by using the power supply circuit ADCL circuits can work with lower power consumption than conventional static CMOS circuit. In this paper, the power supply circuit is improved so that the power consumption can be reduced. Also, it is shown by some experiments that by using the circuit, ADCL circuits can work with lower power consumption than before Improving.

We analyzed the cross-shaped microstripline-fed slot antenna with the reflector using FDTD(Finite-Difference Time-Domain) method in this paper. The proposed antenna uses RR Duroid-5880 substrate(relative permittivity 2.2 and height(1.578 mm) of dielectrics), and compares the optimized results of other kind substrates. The maximum bandwidth of the proposed antenna is from 1.91 GHz to 5.21 GHz, which is approximately 1.437 octave for the VSWR $\leq$ 2. It was found that the bandwidth of the antenna depend highly on the length of the horizontal and vertical feedline as well as the offset position of the feedline. The experimented data for the VSWR and the radiation pattern of the antenna are also represented.

In this paper, we proposed a PLL with the clock count type frequency detector, in which the very fast pull-in time can be realized by resetting the VCO at the rising of input signal after charging the capacitor of loop filter with the voltage corresponding to the frequency of the input signal.

A level of integration will increase, if the number of elements of the circuit can be reduced. We aim to design the circuit of the new system for any further integration by using Neuron MOS Transistor. In this paper, we consider to introduce Soft-Hardware Logic and multiple-valued logic to the design methods for reducing the number of elements and inner wiring. We have designed 4-valued add-subtracter circuit using above logic. We discuss the design methods, features, and characteristics of this circuit by SPICE simulation.

It is possible to perform the digital fuzzy logical high-speed and high-precision computation by the use of redundantly-represented binary positive-digit number arithmetic operation. In this paper, as basic operation circuits in the fuzzy logic new voltage-mode 4-valued binary parallel processing operation circuits using positive redundantly-expressed binary-coded numbers is discussed.

The U-slot patch antenna has been found experimentally to provide impedance and gain bandwidths. Experiment and simulation results include impedance bandwidth, copolar and crosspolar-pattern characteristics and gain measurements. If one of the parameters such as patch width or feed position is varied, U-slot patch can also function as a dual-frequency antenna.

In this paper, we discuss an efficient steady-state analysis of reactance oscillators having multiple oscillations. Our oscillator is consisted of the Cauer or Foster reactance sub-circuit and a negative resistor such as tunnel diode. The reactance circuit has many resonance and antiresonance points on the frequency response curve. Such a circuit having the specified resonance and anti-resonance points can be easily synthesized with the fundamental circuit theory. In this case, the multiple oscillations may occur near at the anti-resonance points. We have developed a user friendly simulator for getting the exact steady state responses using the SPICE.

This paper introduces a voltage-mode biquadratic circuit using only Operational Amplifiers (OTAs) and Operational Transconductance Amplifiers (OTAs). The proposed circuit can realize low-pass, band-pass, high-pass, band-stop and all-pass transfer functions by suitably choosing the input and output terminals. And the circuit characteristics can be electronically tuned through adjusting the transconductance gains of OTAs. Some examples are given together with simulated results by PSpice. The circuit configuration is very suitable for implementation in both bipolar and CMOS technologies.

In this paper, a discrete-time S-dimensional chaos circuit (S = 1,2,3,4,...) with array structure is proposed. By employing array structure which consists of 1-dimensional chaos circuits, the proposed circuit can achieve long working-life. This feature is favorable to exploit as a building block of chaos application systems to get into home electric appliances. Further more, the proposed circuit synthesized using switched-current (SI) techniques is suitable for integration. Concerning the proposed circuit, SPICE simulations are performed. SPICE simulations showed that the proposed circuit can generate the chaotic signals in spite of the fault of the building blocks of the proposed circuit. The proposed circuit is integrable by a standard BiCMOS technology.

In this paper, a new algorithm for adaptive IIR filters based on equation error methods using the RLS algorithm is proposed. In the proposed algorithm, the concept of feedback of the scaled output error proposed by tin and Unbehauen is employed and the forgetting factor is varied in adaptation process for avoiding the accumulation of the estimation error for additive noise . The proposed algorithm has the good convergence property without the parameter estimation error under the existence of mea-surement noise.

The purposes of this paper are to clarify the influences of artifacts on a cerebrovascular audiospectroscopy (CeVASS) and to improve the detecting precision of the CeVASS. First, we perform the CeVASS in 15 healthy adults with various measuring positions such as forehead eyes, cervical parts, temple parts, and occipitomastoid parts, and the influences of artifacts on each position is estimated. Next, we discuss about the removal of the artifacts using cross-spectral analysis. Finally, we propose an improved system of the CeVASS.

It is well known that a Frequency Domain Adaptive Filter (FDAF) converges faster than a Time Domain Adaptive Filter (TDAF) even when the input signal is colored such as a speech signal. We have proposed the FDAF using the Modified Discrete Fourier Transform Pair (MDFTP) and its realization and effectiveness has been confirmed through the computer simulations. In this paper, we apply the FDAF using the MDFTP to the noise cancellation system. The proposed system is based on the Adaptive Line Enhancer (ALE) and utilizes single microphone; therefore it is suitable for the portable electronic equipment. Moreover, we propose to utilize the MDFT for detecting of the pitch in the speech because the number of data points in the MDFT must be equal to the pitch to confirmed that the noise can be removed to near the level of SNR.

AAL2 has been adopted for bandwidth-efficient trans-mission of low bit tate traffic over ATM networks in ITUT and ATM Forum. Since ATM/AAL2 is expected to be used as a switching technology in third-generation mobile access networks and mobile data traffic is expected to increase rapidly in near future, there must be a need for efficient scheduling scheme satisfying the QoS requirement of ow bit rate voice as well as the one of high bit rate data. In this paper, we propose a new class-scheduling scheme to improve data packet loss probability, while Qos of voice traffic is guaranteed, when data traffic is multiplexed together with mobile voice traffic into a single ATM VCC. The proposed scheme can efficiently support data traffic by assigning a time threshold value to voice traffic. Through simulation study, we show that the proposed scheme does not only achieve better efficiency for providing both mobile voice and data services than HOL class-scheduling scheme and normal FIFO scheme, but also guarantees mean voice packet delay under a certain criteria.

A portable equipment that measures a current and voltage waveform of power transmission lines is pro-posed. In the equipment, the current and voltage, respectively, are detected by a loop coil and a capacitor clamped around the power lines. The detected data is transmitted by an FM wave to the receiver on the ground station. Since the receiver is isolated from the power lines, we do not require high potential insulators for the measurement of current and voltage. The proposed equipment is therefore, small-sized, light, and low in the cost of production. Experimental results presented here show that the equipment can monitor the current flowing in single wire over a ground plane and the potential of the wire.

We have proposed a simple method based on IIR filters for realizing sound image localization. How-ever the nonlinearity of phase characteristics of the IIR filters, which are used for sound image localization, cause decrease of the localization accuracy. In this paper we investigate the influence of phase characteristics on the sound localization. Head-related transfer functions (HRTFs) of a dummy-head are approximated by the IIR filter. We carried out sound image localization experiment with 2-loudspeaker reproduction using the approximated HRTFs. Then the errors which obtained from experiments were compared with the theoretical values which were estimated from the phase shifts of the IIR filters. As a result there was little influence of the nonlinear phase characteristics of the IIR fitters in the localization on the horizontal plane.

This paper addresses a new method of blind source separation (BSS) when sources are nonstationary signals. Our method requires only multiple correlation matrices of the observed data at several time-windowed data frames to estimate the mixing matrix. In contrast to most existing BSS methods where higher-order statistics is necessary, our method is based on only second-order statistics. In the framework of correlation matching, we develop a new BSS algorithm. The useful behavior of the proposed method is verified by numerical experiments.

This paper proposes a cooperative parallel tabu search which incorporates with the historical information exchange among processors in addition to its own searching of each processor. We investigate the influence of our proposed cooperative parallel tabu search by comparison with a serial tabu search. We also propose two extensions of the cooperative parallel tabu search which are the cooperative construction of tabu memory and the selection of cooperative partner. Through computational experiment, we observe the improvement of solutions by our proposed method.

An experimental multimodal system combining natural input modes such as speech, lip movement, and gaze is proposed in this paper. It benefits from novel human-compute. interaction (HCI) modalities and from multimodal integration for tackling the problem of the HCI bottleneck. This system allows the user to select menu items on the screen by employing speech recognition, lip reading, and gaze tracking components in parallel. Face tracking is a supplementary component to gaze tracking and lip movement analysis. These key components are reviewed and preliminary results are shown with multimodal integration and user testing on the prototype system. It is noteworthy that the system equipped with gaze tracking and lip reading is very effective in noisy environment, where the speech recognition rate is low, moreover, not stable. Our long term interest is to build a user interface embedded in a commercial car navigation system (CNS).

This paper describes a DSP implementation of a real-time 3D sound localization algorithm with the use of a low power embedded DSP. A distinctive feature of this implementation is that the audible frequency band is divided into three, in accordance with the sound reflection and diffraction phenomena through different media from a certain sound source to human ears, and then in each subband a specific implementation procedure of the 3D sound localization is devised so as to operate real-time at a low frequency of 50MHz on a 16bit fixed-point DSP. Thus out DSP implementation can provide a listener with 3D sound effects through a headphone at low cost and low power consumption.

In this paper, a word-unit recognition is performed to implement a speech recognition system over the web, using JAVA Applet and continuous distributed HMM. The system based on Client/server model is designed. A client computer processes speech with Applet, and then transmits feature parameters to the server computer though the Internet. The speech recognition system in the server computer transmits the result applied by the forward algorithm to the client computer and the result is displayed in the client computer by text.

A technique that uses linear prediction to achieve noise reduction in a voice signal which has been mixed with an ambient noise (Signal to Noise (S-N) ratio = about 0dB) is proposed. This noise reduction method which is based on the linear prediction estimates the voice spectrum while ignoring the spectrum of the noise. The performance of the noise reduction method is first examined using the transversal linear predictor filter. However, with this method there is deterioration in the tone quality of the predicted voice due to the low level of the S-N ratio. An additional processing circuit is then proposed so as to adjust the noise reduction circuit with an aim of improving the problem of tone deterioration. Next, we consider a practical application where the effects of round on errors arising from fixed-point computation has to be minimized. This minimization is achieved by using the lattice predictor filter which in comparison to the transversal type, is Down to be less sensitive to the round-off error associated with finite word length operations. Finally, we consider a practical application where noise reduction is necessary. In this noise reduction method, both the voice spectrum and the actual noise spectrum are estimated. Noise reduction is achieved by using the linear predictor filter which includes the control of the predictor filter coefficient’s update.

This paper describes a real-time 3D sound localization algorithm to be implemented with the use of a Bow power embedded DSP. This algorithm first divides the audible frequency band into three, on the basis of the analysis of the sound reflection and diffraction effects through different media from a certain sound source to human ears, and then in each subband a specific procedure is devised fur the 3D sound localization so as to operate real-time on a low power embedded DSP This algorithm aims at providing a listener with the 3D sound effects through a headphone at low cost and low power consumption.

A signaling system for a single-track railroad has been specified in CafeOBJ. In this paper, we describe the specification of arbitrary two adjacent stations connected by a single line that is called a two-station system. The system consists of two stations, a railroad line (between the stations) that is also divided into some contiguous sections, signals and trains. Each object has been specified in terms of their behavior, and by composing the specifications with projection operators the whole specification has been described. A safety property that more than one train never enters a same section simultaneously has also been verified with CafeOBJ.

Linear discriminant analysis (LDA) is a basic tool of pattern recognition, and it is used in extensive fields, e.g. face identification. However, LDA is poor at adaptability since it is a batch type algorithm. To overcome this, a new algorithm of online LDA is proposed in the present paper. It is experimentally shown that the new algorithm is about two times faster than the previously proposed algorithm.

Matching pursuit algorithm is a signal expansion technique whose efficiency for motion compensated residual image has already been demonstrated in the MPEG-4 framework. However, one of the practical concerns related to applying matching pursuit algorithm to real-time scalable video coding is its massive computation required for finding dictionary elements. In this respective, this paper proposes a fast algorithm, which is composed of three sub-methods. The first method utilizes the property of symmetry in 1-D dictionary element and the second uses mathematical elimination of inner product calculation in advance, and the last one uses frequency property of 2-D dictionary. Experimental results show that our algorithm needs about 30% computational load compared to the conventional fast algorithm using separable property of 2-D gabor dictionary with negligible quality degradation.

Three representations are known to implement the discrete wavelet transform (DWT) ; i.e., direct, lifting and matrix forms. In these representations, direct and lifting forms are well known so far. This paper derives the matrix form of the DWT from the direct form. Then, we implement these three representations on a programmable digital signal processor (in the following, DSP processor) and compare them in terms of the number of calculations and instruction cycles. As a result, we confirm that the lifting form has the lowest number of calculations and cycles, and the matrix form has an effective decrease in the number of cycles than other representations on the DSP processor.

We propose two new algorithms for parallelism-independent scheduling. The machine code generated from the compiler using these algorithms in its scheduling phase is parallelism-independent code, executable in minimum time regardless of the number of the processors in the parallel computer. Our new algorithms have the following phases: finding the minimum number of processors on which the program can be executed in minimal time, scheduling by an heuristic algorithm for this predefined number of processors, and serialization of the parallel schedule according to the earliest start time of the tasks. At run time tasks are taken from the serialized schedule and assigned to the processor which allows the earliest start time of the task. The order of the tasks decided at compile time is not changed at run time regardless of the number of the available processors which means there is no out-of-order issue and execution. The scheduling is done predominantly at compile time and dynamic scheduling is minimized and diminished to allocation of the tasks to the processors. We evaluate the proposed algorithms by comparing them in terms of schedule length to the CP/MISF algorithm. For performance evaluation we use both randomly generated DAGs (directed acyclic graphs) and DACs representing real applications. From practical point of view, the algorithms we propose can be successfully used for scheduling programs for in-order superscalar processors and shared memory multiprocessor systems. Superscalar processors with any number of functional units can execute the parallelism-independent code in minimum time without necessity for dynamic scheduling and out-of-order issue hardware. This means that the use of our algorithms will lead to reducing the complexity of the hardware of the processors and the run-time overhead related to the dynamic scheduling.

Among the multi-dimensional query types, ranking query is needed if we want the object one by one until we satisfy for the result. In multi-dimensional indexing structures like R-tree or its variants, not many methods are introduced in this area. In this paper, we introduce new ranking query processing algorithm which use the filtering mechanism in the R-tree variants.

We discuss the iterative methods for linear systems on a single processing node of the HITACHI SR8000. Each processing node of the SR8000 is a shared memory parallel computer which is composed of eight RISC processors with a pseudo-vector facility. We implement highly optimized codes for basic linear operations including a matrix-vector product and apply them to the conjugate gradient (CG) and the conjugate residual (CR) methods for linear systems. Our tuned codes for both method score nearly 50% of the theoretical peak performance, which is the best in the sense that it corresponds to an asymptotic performance of the inner product.

This paper proposed an optimal register resource allocation algorithm using graph coloring for minimal register at high level synthesis. The proposed algorithm constructed interference graph consist of the intermediated representation CFG to description VHDL. and at interference graph fur the minimal select color selected a position node at stack, the next inserted spill code and the graph coloring process executes for optimal register allocation. The proposed algorithm proves to effect that result compare another allocation techniques through experiments of bench mark.

We developed an electronic music glove (EMG) system that could play musical scores in real time processing. The EMG system interfaces with the signal coming from the controller to the sound card in the computer. The computer, according to the status of the finger and foot switches, generates the signals to the speaker systems using the application C++ program by making use of MIDI message. The EMG systems can control up to several octave notes and duration of sound, and several musical performance expressions such as chorus, reverberation, rhythm, and volume. Finally, our EMG could play the performance of simple music depending on the choice of any kind of musical instruments in the sound card in computer systems.

This paper presents a new scheduling method for ILP processing called NHS(Novel Hybrid Scheduling). It concerns not only exploiting as much ILP as possible like other state-of-the-art scheduling scheme, but also choosing the most important instructions among many ready-to-execute instructions to processors in order to reduce the execution time under limited hardware resource. At the heart of NHS is a conception called CCP(Complex Critical Path), an extension of CP(Critical Path). By using CCP, compiler not only can get a global information of the whole program to extract ILP, but also can collecting data dependence information and control flow information. The paper also presents the simulation results, to date, of our attempts to study the NHS scheduling method. The results indicate good potential for this scheduling method.

Cluster system provides attractive scalability in terms of computation power and memory size. With the advances in high speed computer network technology, cluster systems are becoming increasingly competitive compared to expensive parallel machines. In parallel processing program, each task load is difficult to predict before running the program and each task is interdependent each other in many ways. Load imbalancing induces an obstacle to system performance. Most of researches in load balancing were concerned with distributed system but researches in cluster system are few. In cluster system, the dynamic load balancing algorithm which evaluates each processor's load in runtime is purpose that the load of each node are evenly distributed. But, if communication cost or node complexity becomes high, it is not effective method for all nodes to attend load balancing process. In that circumstances, it is good to reduce the number of node which attend to load balancing process. We have modeled cluster systems and proposed marginal dynamic load balancing algorithms suitable for that circumstances.

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fie2, degree of uk terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for perform above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesize ${\alpha}$$\^$k/ generation module and control signal CSt generation module with A-cell and M-cell. Then, we propose the future research and prospects.

In a batch scheduling policy being different from real video system, the requests are not served immediately due to grouping user's requests upon every scheduling points. Such waiting delays by inefficient managements makes an unfair service to users and increases the possibility of higher reneging rates. This paper proposes an adaptive batch scheduling scheme which reduces the average waiting time of user’s requests and reduces the starvation problem for requesters of less popular movies. The proposed scheme selects dynamically multiple videos in given intervals based on the service patterns which reflect the popularity distribution and resource utilizations. Experimental simulation shows that proposed scheme improves about 20-30 percent of average waiting time and reduces significantly the starving requesters comparing with those of conventional methods such as FCFS and MQL.

The paper proposes the scheme of skew detection for Thai printed document images by using linear regression algorithm. It intends to use with the Thai character recognition systems to reduce the skew detection time. This scheme begins by finding the center of gravity of a document image. This point is used as the starting point for gathering data in the scheme. The data is obtained by scanning incrementally one pixel in vertically with the width of 20-pixels. After the scanning process, if data Is different from it's neighbor more than ${\pm}$ 15 pixels, it will be considered as noise or data in other lines and will be deleted. The last step is the operation by using linear regression algorithm on these selected data and the skew angle will be obtained. The proposed method has been tested with 45 document images with different fonts, sizes and skew angles. The experiment results show that the proposed method can detect the skew angle with the error of less then one degree. The average processing time is about 19 times faster than that of the Hough Transform method.

Research interests on temporal data have been almost focused on data models. There has been relatively less research in the area of temporal data management. In this paper, we propose two data migration strategies based on time-segmented storage structure: the migration strategy by Time Granularity, the migration strategy by LST-GET. We describe the criterion for data migration and moving process. We simulated the performance of the migration strategy by Time Granularity in order to compare it with non-segmentation method. We compared and analyzed two data migration strategies for temporal data.

We discuss the direct methods (Gauss-Jordan and Gaussian eliminations) to solve linear systems on distributed memory parallel computers. It will be shown that the so-called row-cyclic storage gives rise to the best performance among the standard three (row-cyclic, column-cyclic and cyclic-cyclic) data storages. We also show that Gauss-Jordan elimination, rather than Gaussian elimination, is highly efficient for the direct solution of linear systems in parallel processing, though Gauss-Jordan elimination requires a larger number of arithmetic operations than Gaussian elimination. Numerical experiment is performed on HITACHI SR12201 with the standard libraries MPI and BLAS.

This paper presented a FPGA design of SEED, which is the Korea standard 128-bit block cipher. In this work, SEED was designed technology- independently for other applications such as ASIC or core-based designs. Hence in case of changing the target of design, it is not necessary to modify design or need only minor modification to reuse the design. Since SEED algorithm requires a lot of hardware resources, each unit was designed only once and used sequentially. So, the number of gates was minimized and SEED algorithm was fitted in FPGA without additional components. It was confirmed that the rate of resource usage is about 80% in ALTERA 10KE and the SEED design operates in a clock frequency of 131.57 MHz and an encryption rate of 29 Mbps.

When a feedback bridging fault is activated, oscillation may be generated in output signal lines. If the oscillation is generated, the fault may not be detected by logic testing. Thus, in the past we proposed a current sensor to detect feedback bridging faults by supply current testing. The sensor circuit design requires the maximum frequency of oscillation which is generated when feedback bridging fault is excited as a specification. In this paper, an estimation method of the oscillation frequency is proposed. Also, it is shown by some experiments that the frequency obtained by the method can be used for the sensor design.

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are fabricated with ternary voltage mode NOR, NAND, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, a lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.25 micron CMOS technology and 2.5 volts supply voltage. The Architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

In the past, we proposed an IDDQ testable design method for static CMOS PLA circuits. All bridging faults can be detected in NOR planes of our testable designed PLA circuits by IDDQ testing with 4 kinds of test input vectors which are independent of the logical functions to be realized. However, the testable designed PLA circuits consume large power in the normal operation. In this paper, a new IDDQ testable design method is proposed and evaluated by some experiments. The experimental results show that the PLA circuit designed with our method can work with low power consumption than the previous one.

In this paper we propose procedures to enhance testability by modifying state transition tables. In these procedures, transitions about undefined states, which are not described in state transition tables but exist in a synthesized gate level circuit, are added to a state transition table. Experimental results for MCNC benchmarks are shown.

In this paper, we propose a test pattern generation algorithm on the basis of the identification of undetectable faults for Speed-Independent(SI) asynchronous control circuits. The proposed methodology generates tests from the specification of a target circuit, which describes the behavior of the circuit in the form of Signal Transition Graph (STG). The proposed identification method uses only topological information of a target circuit and reachability information of a fault-free circuit, which is generated in the form of Binary Decision Diagram(BDD) during pre-processing. Experimental results show that high fault coverage over single input stuck-at fault model is obtained for several synthesized SI circuits and the use of the identification process as a preprocessing decreases execution time of the proposed test generation with negligible costs.

This paper describes reconfiguration methods for processor arrays as a fault tolerance technique at the fabrication time. First, we show that any method based on a conventional idea cannot achieve optimal in reconfigurability. Then, we present two types of methods based on a new idea, that is sequential routing. The one is optimal in reconfigurability, and the other is advantageous in time complexity.

It is shown that $I_{DDQ}$ testing is very useful for shipping fault-free CMOS ICs. However, test time of $I_{DDQ}$ testing is extremely larger than one of logic testing. In this paper, a new test input sequence generation methodology is proposed to reduce the test time of $I_{DDQ}$ testing. At first, it is Shown that $I_{DDQ}$ test time Will be denominated by charge supply current for load capacitance of gates whose output logic values are changed by test input vector application and the charge current depends on input sequence of test vectors. After that, a test input sequence generation methodology is proposed. The feasibility is checked by some experiments.riments.

This paper proposes a 16-bit ${\times}$ 16-bit multiplier for 2 twos-complement binary numbers with tree-like structure and implements it on a FPGA. The space and time complexity analysis shows that the 16-bit Tree-like multiplier represents lower circuit complexity and computes more quickly than both Booth array multiplier md Modified array multiplier.

This paper discusses on application of meta-heuristic algorithms such as the genetic algorithm (GA) and the simulated annealing (SA) to the LSI module placement. We propose useful crossover method for improving of searching capability in genetic algorithm. By using our proposed crossover method, we have been able to keep good schemata in the chromosome and the variety of the solution. From the experimental results, we have obtained better result than the simulated annealing method by starting from the initial placement of the min-cut method.

We designed a self-timed interface circuit for efficient communication in IP (Intellectual Property)-based system with high-speed self-timed FIFO and a set of self-timed event logic library with 0.25um CMOS technology. Optimized self-timed standard cell layouts and Verilog models are generated for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. With clock control method and FIFO, we implemented high-speed 32bit-interface chip for self-timed system, which generated maximum system clock is 2.2GHz. The size of the core is about 1.1mm x 1.1mm.

There are some variations in quiescent supply current or TTL SSIs. Thus, some variations in quiescent supply current of logic circuits made of TTL SSIs will be generated. The variations make it difficult to apply supply current test methods to tests of TTL circuits. In this paper, in order to examine the applicability to R circuits, fault coverages of a supply current test method for open faults in some ISCAS-85 benchmark circuits are evaluated, Which are made of TTL LS-type SSIs. The experimental results shows that if SSIs are used for implementation having the variation of quiescent supply current within 1%, supply current test methods are applicable for the tests.

This paper proposes an efficient and accurate power estimation method for Application Specific Instruction set Processors (ASIPs). Proposed method takes advantage of the data types of variables in application program to be executed on the ASIP. According to the experimental results, the efficiency of proposed method was more than 1000 times as high as that of conventional RTL based power estimation method, and the estimation error was within 10% compared to a conventional gate-level accurate power estimation method

In this paper four lossy and one lossless inductance simulator topologies employing a single DO-OTA are presented. For the topologies proposed the inductance $L_{eq}$ and the series resistance $R_{eq}$ are independently adjustable. The topologies employ a single capacitor and are canonic in the number of capacitors. The resistors in the topologies can easily be implemented also with DO-OTAs. In this case the topologies proposed change to DO-OTA-C inductor simulators which is important from the integration point of view. Simulation results are included to verify theory.

The method of Variable Structure Control (VSC) design of windmill power systems is proposed. In the design of sliding mode control, we use Riccati equations arising in linear H$\^$$\infty$/ control to decide a stable sliding surface. Then the reachability to the sliding surface is realized by designing a nonlinear controller for the windmill power system. The capability of the proposed controller to damp out the oscillations of power and the robustness with respect to the system parameter variations and model errors are evaluated in the simulation study.

The reduction of chip area and delay is important purpose of Scheduling in High-Level Synthesis. This paper presents a scheduling approach with component selection. After obtaining a initial schedule taking only single-functional u-nits, the component selection of our approach attempts the reduction of chip area and/or delay by the selection more suitable components in a component library using Simulated Annealing.

This paper describes a single transistor type ferroelectric field effect transistor (1Tr FeFET) memory cell scheme, which select one unit memory cell and program/read it. The well voltage can be controlled by isolating the common row well lines. Through applying bias voltage to Gate and Well, respectively, we implement If FeFET memory cell scheme in which interference problem is not generated and the selection of each memory cell is possible. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

This paper proposes a method that enables us to implement the recursive least squares (RLS) algorithm at, high throughput rate using fewer processing elements (PEs). It is known that the pipeline processing can provide a high throughput rate. But, pipelining is effective only when enough number of PEs are available. The proposed method achieves high throughput rate using a few PEs. The effectiveness of the proposed method is verified through simulations on programmable digital signal processors (in the following, DSP processors).

This paper suggests a methodology in which control signals for high-level synthesis are generated from SDL specification. SDL is based on EFSM(Extended Finite State Machine) model. Data path and control part are partitioned into representing data operations in the from of scheduled data flow graph and process behavior of an SDL code in forms of an abstract FSM. Resource allocation is performed based on the suggested architecture model and local control signals to drive allocated functional blocks are incorporated into an abstract FSM extracted from an SDL process specification. Data path and global controller acquired through suggested methodology are combined into structural VHDL representation and correctness of behavior for final circuit is verified through waveform simulation.

We investigate potential advantages and problems when a superscalar processor is designed and implemented using asynchronous design methods. Conventional techniques of superscalar processing are applied and data dependent adder is considered as an asynchronous component. Intensive simulations on SPEC INT95 benchmark suites are made for the purpose of performance comparison between a synchronous and an asynchronous superscalar processor, respectively. The simulation results show about 5% speedup with asynchronous design methods in the sense of Issue Rate.

This paper describes the innovation of VLSI design methodology in the coming decade. Technology trend of VLSI fabrication is surveyed first. Then the so-called “design crisis” is analyzed. Finally, possible design methodology to overcome the design crisis is discussed.

In this paper, we propose a window warping method to solve stereo matching problems in projective distortion region. Because the projective distortion region cant t be estimated with fixed-size block matching algorithm, we use the window warping technique in block matching process. The position of a reference window to resample is obtained adaptively according to the degree of reliability in disparity estimated previously. The initial disparity and reliability are obtained by applying a well known hierarchical strategy. The experimental result shows that considerable improvement is obtained in the projective distortion region.

In this paper, we propose a new method based on SA(simulated annealing) with a fast algorithm for 3D image reconstructrion from the coded apereture images. The reconstructed images can be significantly improved by SA and to large computation cost of SA can be significantly reduced by the fast algorithm.

The new MPEG-4 video coding standard enables content-based functionalities. In order to support the philosophy of the MPEG-4 visual standard, each frame of video sequences should be represented in terms of video object planes (VOP’s). In other words, video objects to be encoded in still pictures or video sequences should be prepared before the encoding process starts. Therefore, it requires a prior decomposition of sequences into VOP’s so that each VOP represents a moving object. A parallel processing system is required an automatic segmentation to be processed in real-time, because an automatic segmentation is time consuming. This paper addresses the parallel processing: system for an automatic segmentation for separating moving object from the background in image sequences. The proposed parallel processing system comprises of processing elements (PE’s) and a multi-access memory system (MAMS). Multi-access memory system is a memory controller to perform parallel memory access with the variety of types: horizontal, vertical, and block access way. In order to realize these ways, a multi-access memory system consists of a memory module selection module, data routing modules, and an address calculation and routing module. The proposed system is simulated and evaluated by the CADENCE Verilog-XL hardware simulation package.

In this paper, we present two types of digital image stabilization (DIS) schemes for mobile video communications. In the first scheme, the DIS system, which is used as a preprocessor of the video encoder, compensates the camera’s undesirable shakes before encoding. This method can reduce the bit rate of encoded video sequence by attenuating the prediction error to be encoded. In the second proposed scheme, the DIS system is coupled with the video decoder. The second scheme uses the K-means clustering algorithm to estimate the camera motion using motion vectors decoded from the received video stream. Simulation results show that the first scheme improves coding efficiency, while the second scheme is computationally efficient since it does not require motion estimation.

This paper proposes a method to improve video quality on images that have blocking artifacts at block boundary. Block image transform coding suffers from blocking artifact that is a main cause of degrading video quality because of the quantization error of transform coefficients in quantization process. filtering and DPCM for DC components have been widely used to reduce blocking artifact. Recently, lots of works focus on the technique that minimizes block effects using discontinuity of block boundaries. In this paper, image blurring in decoding stage is improved by adding compensation factor to each transformed blocks so that discontinuity of block boundaries can be decreased. The compensation factor is applied on each block without much loss of edge components.

This study is to segment white matter, gray matter, and cerebrospinal fluid(CSF) on a brain MR image of coronal section and to calculate the volume of each. First, we segmented the whole region of a brain from a black colored background, a skull and a fat layer. Then, we calculated the partial volume of each component, which was present in scanning finite thickness, with the arithmetical analysis of gray value from the internal region of a brain showing the blurring effects on the basis of the MR image forming principle. Calculated partial volumes of white matter, gray matter and CSF were used to determine the threshold for the segmentation of each component on a brain MR image showing the blurring effects. Finally, the volumes of segmented white matter, gray matter, and CSF were calculated. The result of this study can be used as the objective diagnostic method to determine the degree of brain atrophy of patients who have neurodegenertive diseases such as Alzheimer’s disease and cerebral palsy.

A direct RTI(Rotation and translation invariant) fingerprint identification is proposed using the GCMs(generalized complex moments) and Gabor filter-based features from the grey level fingerprint around core point. The core point is located as reference point for the translation invariant matching. And its symmetry axis is detected for the rotation invariant matching from its neighboring region centered at the core point. And then, fingerprint is divided into non-overlapping blocks with respect to the core point and, in contrast to minutiae-based method using various processing steps, features are directly extracted from the blocked grey level fingerprint using Gabor filter, which provides information contained in a particular orientation in the image. The Proposed fingerprint identification is based on the Euclidean distance of the corresponding Gabor features between the input and the template fingerprint. Experiments are conducted on 300 ${\times}$ 300 fingerprints obtained from the CMOS sensor with 500 dpi resolution, and the proposed method could obtain 97% identification rate.

In this paper, an automated segmentation algorithm is proposed for MR brain images using T1-weighted, T2-weighted, and PD images complementarily. The proposed segmentation algorithm is composed of 3 steps. In the first step, cerebrum images are extracted by putting a cerebrum mask upon the three input images. In the second step, outstanding clusters that represent inner tissues of the cerebrum are chosen among 3-dimensional (3D) clusters. 3D clusters are determined by intersecting densely distributed parts of 2D histogram in the 3D space formed with three optimal scale images. Optimal scale image best describes the shape of densely distributed parts of pixels in 2D histogram. In the final step, cerebrum images are segmented using FCM algorithm with it’s initial centroid value as the outstanding cluster’s centroid value. The proposed segmentation algorithm complements the defect of FCM algorithm, being influenced upon initial centroid, by calculating cluster’s centroid accurately And also can get better segmentation results from the proposed segmentation algorithm with multi spectral analysis than the results of single spectral analysis.

In this paper, an efficient rate control algorithm based on rate prediction is proposed for maintaining a smooth buffer variation and a small buffer size. The proposed method adjusts the quantization scaling factor by using the predicted bit-rate to meet the target bit budget exactly. Experimental result show that the proposed prediction-based rate control scheme can regulate the bit-rate across scene changes more effectively and achieve better PSNR performance than existing rate control mechanisms such as the MPEG-2 Test Model 5 (TM5) and the Adaptive Scene Analysis (ASA).

Variable length codes are often used in entropy coding, but are very vulnerable in noisy environments. Reversible variable length codes, however, muse possible to decode instantaneously in both forward and backward directions, so that more usable data can be retrieved when bit errors occur via transmission. Furthermore, partial decodability is desirable to introduce in the reversible variable length code because ROI (Region Of Interest) decoding function is sometimes required in recent image information systems such as the medical imaging, the digital museum and so on. In this paper, we propose a partially decodable and reversible variable length code by modifying Golomb-Rice code.

It is important to compress three dimensional (3D) data efficiently, since 3D data are too large to store or transmit in general. In this paper, we propose a lossless compression algorithm of the 3D mesh connectivity, based on the vertex degree. Most techniques for the 3D mesh compression treat the connectivity and the geometric separately, but our approach attempts to exploit the geometric information for compressing the connectivity information. We use the geometric angle constraint of the vertex fanout pattern to predict the vertex degree, so the proposed algorithm yields higher compression efficiency than the conventional algorithms.

In this paper, a watermarking technique for digital images is proposed. In our method, an image is 1-1eve1 wavelet transformed, and then the watermark of a binary stamp is embedded into the baseband. The watermark is embedded by inverting the polarities of the selected coefficient pairs. In the inverting process, we can increase perceptual image quality by finding means and differences of the selected neighboring coefficient pairs, and then adding values, which are inversely proportional to the differences, to the means. The experimental results show that the proposed method has good quality and is robust to JPEG lossy compression and various image processing operations.

Digital watermarking is a technical solution to the copyright problem and is a necessary technique to protect copyright of multimedia content. Recently, there are many digital watermarking methods that deal in grey scale still images. However, only a few researchers are interested in digital watermarking fro video and color images. In this paper, we focus on digital watermarking for color images. At first, in order to embed the watermark signal in color image, we converted RGB color space to YCbCr color space which is a world-wide digital component video standard. In addition, we adopted the acceptable degree of color difference in order to keep the invisibility.

This paper presents an algorithm for simplification of 3D triangular mesh data, based on mesh simplification. The proposed algorithm is first attempt to segment the entire mesh into several parts using the orientation of triangles. Then simplification algorithm is applied to each segment that has similar geometric property. The proposed two step multi-resolution modeling scheme would yield better performance then conventional algorithm like edge collapse technique, since the segmentation step can give global information on the input shape. The experimental results show that the proposed algorithm is performed efficiently.

In this paper, we propose a joint coding system for still images using source coding and powerful error correcting code schemes. Our system comprises an LVQ (lattice vector quantization) source coding for wavelet transformed images and turbo coding for channel coding. The parameters of the image encoder and channel encoder have been optimized for an n-D (dimension) cubic lattice (D$_{n}$, Z$_{n}$), parallel concatenation fur two simple RSC (recursive systematic convolutional code) and an interleaver. For decoding the received image in the case of the AWGN (additive white gaussian noise) channel, we used an iterative joint source-channel decoding algorithm for a SISO (soft-input soft-output) MAP (maximum a posteriori) module. The performance of transmission system has been evaluated in the PSNR, BER and iteration times. A very small degradation of the PSNR and an improvement in BER were compared to a system without joint source-channel decoding at the input of the receiver.ver.

A modified watershed transform is proposed which is context-free marker-controlled and minima imposition-free to reduce the over-segmentation and to speedup the transform. In contrast to the conventional methods in which a priori knowledge, such as flat zones, zones of homogeneous texture, and morphological distance, is required for marker extraction, context-free marker extraction is proposed by using the attention operator based on the GST (generalized symmetry transform). By using the context-free marker, the proposed watershed transform exploit marker-constrained labeling to speedup the computation and to reduce the over-segmentation by eliminating the unnecessary geodesic reconstruction such as the minima imposition and thereby eliminating the necessity of the post-processing of region merging. The simulation results show that the proposed method can extract context-free markers inside the objects from the complex background that includes multiple objects and efficiently reduces over-segmentation and computation time.

Because of the great variety of demands on real-time scheduling, real-time kernel should be small, fast and predictable. In this paper, we present that Real-time applications should be split into small and simple parts with hard real-time constraints. Following this concept, we have designed and implemented to have the properties of both hard real-time kernel and general kernel. And, to prove be useful the proposal kernel, we compare and analyze the performance with RT-Linux 0.5a

We study the problem of designing at minimum cost a two-connected network topology such that the shortest cycle to which each edge belongs does not exceed a given maximum number of hops. This problem is considered as part of network planning and arises in the design of backbone networks. We propose a genetic algorithm approach that uses a solution representation, in which the connectivity and ring constraints can be easily encoded. We also propose a crossover operator that ensures a generated solution is feasible. By doing so, the checking of constraints is avoided and no repair mechanism is required. We carry out experimental evaluations to investigate the solution representation issues and GA operators for the network design problem.

In this paper, we compare the bit-error-rate performance of the fast-frequency-hopped spread-spectrum multiple-access (FFH/SSMA) and direct-sequence code-division multiple access (DS/CDMA) systems in a Rician fading channel. Each system has a same data rate, bandwidth and transmits over a Rician fading channel. The results illustrate tradoffs in performance between the FFH/SSMA and DS/CDMA systems as a function of the parameters such as average signal to noise ratio and processing gain. The performance of the FFH/SSMA system is shown to be less sensitive to the change of fading environments, while the change of processing gain and average signal to noise ratio gives considerable affect to the FFH/SSMA system compared with the DS/CDMA system. Without respect to the change of system parameters, for most of Rician fading channels (except non-fading channel), FFH/SSMA system gives better performance than DS/CDMA system in BBR < 10$\^$-3/.

In this paper, performance of a pseudonoise (PN) code tracking loop is analyzed and simulated for a direct-sequence/code-division multiple access ( DS/CDMA) system with imperfect power control in a multipath fading channel. A noncoherent first-order delay-locked loop (DLL) is considered as a PN code tracking loop. Power control error is modeled as a log-normally distributed random variable. From the simulation results, it is shown that for smaller discriminator offset, tracking jitter performance is improved while MTLL performance is degraded. It is shown that large power control error and heavy shadowing substantially degrade the PN tracking performance. The analysis in this paper can be applicable to design of PN code tracking loop for a DS/CDMA system.

We discuss simulation results concerning the performance of the TCP protocol when running over high-speed HFC networks. Hybrid Fiber Coaxial are likely to provide fast and cost effective sup-port to a variety of applications including Video on demand, interactive computer games, and internet-type applications such as Webbrowsing, ftp, and telephony. Since most of these applications, use TCP as the transport later protocol, the key to their success largely depends on the effectiveness of the TCP protocol. In all simulation scenarios the TCP traffic is maxed with some background traffic whose level is taken as a variable parameter. Both the background traffic and TCP traffic are either unshaped, or shaped according to the GCRA algorithm. The effect of the background traffic on the TCP protocol performance is discussed varying the buffering capacity with nodes as well as the peak bit rate that each TCP connection is allowed to use.

In this paper, the RBF-based multiuser detector (MUD) is proposed for a multirate DS/CDMA system. The performance of RBF-based MUD is compared with that of many suboptimal multiuser detectors in terms of bit error probability. From the simulation results, it is confirmed that the RBF-based multiuser detector outperforms decorrelating detector, and achieves near-optimum performance in several situations. The results in this paper can be applied to design of MUD fur a multirate DS/CDMA system.

In this paper, we investigate the effect of the retransmission limit both the system capacity and the average number of retransmissions in a voice/data DS-CDMA system. Basically, we consider the IS-95 type reverse link of the CDMA system, which supports two kinds of services: a general voice and a packetized data service. ARQ is used for the reliable data transmission. Convolutional code is used for FEC and CRC-CCITT code is used for the error detection in ARQ. The result shows that the number of concurrent data users decreases as we reduce the number of the retransmissions. However, at the same time, we can also reduce the average number of retransmissions. Concluding1y, we can select the retransmission limit so as to reduce large amount of' retransmissions with small sacrifice in the system capacity.

This paper deals with the statistical analysis of an autocalibration procedure for the gain and phase imbalances between the in-phase (I) and quadrature (Q) components in quadrature receivers. In real implementation, the imbalances of the gain and phase exist and degrade the performance of the receiver. In this paper we investigate the statistical characteristic of the estimates in an on-line imbalance estimation method for the receiver under the assumption of an additive white Gaussian noise environment.

It is well known that the OFDM system is weak against the frequency offset. The frequency offset attenuates the received signal power and makes the performance bound in the OFDM transmission. We show the performance bound of the OFDM transmission with the frequency offset under the additive white Gaussian noise channel by the numerical method. According to the results, increasing the transmitting power is not useful to improve the performance, when the frequency offset exits. The performance degradation is very severe as the frequency offset increases.

According to the development of B-ISDN on ATM network, the uses of Multimedia service is growing. Although ABR service uses the network resource most effectively because it is able to change the transfer rate, it is not used for multimedia service until recently. In this paper, we set priority queue and non-priority queue in the ATM switch and each queue has threshold so is can be adopted in different transfer rate method. We propose the real-time traffic transfer method over ABR service based on an effective traffic control method.

This paper addresses how to be connected with end-to-end shortcut using ATM Switched Virtual Connection (SVC) in ATM-based Multi-Protocol Label Switching (MPLS) Networks. Without additionally existing ATM Ships-in-the-Night (SIN) mode, when the stream is continuously transmitted at the same destination with the lapse of determined aging time, the connection is changed with end-to-end shortcut connection using ATM signaling. An ATM direct short circuit is performed an IP and ATM effective integration. An ATM shortcut has a number of advantages, like higher throughput, shorter end-to-end delay, reduced router load, better utilization of L2 Quality of Service (QoS) capabilities, and route optimization. In particular between other MPLS domains, this can be efficiently improved the performance of networks.

In this paper, we proposed high performance packet forwarding engine for asynchronous transfer mode(ATM) based gigabit routers. The forwarding engine is based on ATM switch and accommodates four 622Mbps ports. The forwarding engine has been designed to be able to process the Intemet protocol(IP) packet at 2.5Gbps using the pipelined If header processing and lookup control mechanism. For high performance packet forwarding, we used content addressable memory(CAM) based routing coprocessor operating in hardware and implemented the pipelined lookup control function into a field programmable gate array(FPGA). The pipelined packet header processing mechanism enhanced the forwarding performance of the If packets ingressed from four different 622Mbps ports. Moreover, the If lookup controller designed to have the performance up to 12.5Mpps. The proposed forwarding engine is also designed to support differentiated services(DS) and multiprotocol label switching(MPLS).

In this paper, we propose and design new architecture of the modified Banyan switch for a high speed networking and the high speed parallel computer. The proposed switching network with a remodeled architecture is a newly modified Banyan network with eight input and output ports. The switch scheme is that two packets may arrive on different inputs destined for the same output. We have analyzed the maximum throughput of the revised switch. The result of the analyses shows good agreement simulation and if we adopt such architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased about lloio when we compare the switching system with the input buffer system. We have designed and verified the switching system in VHDL.

This paper presents a multitier GIS architecture to adapt to large-scale distributed networks and to improve data transfer performance with intelligent caching technique. We design this system using UML based on object-oriented analysis. We show some advantages in our proposed system against the ordinary GIS, in special, suitability to distributed networks.

A fundamental tenet of CBD is that a component has a specification which describes what that component does, and how it behaves when its services are used. In general, the implementation may be written in a different programming language and execute on different technology platform, from the language and platform used by the client program. In order to implement practically the system that is designed by the Farmer model, there is need to have the ISM (Interface Specification Model) which explains specification about the functions of entities of the Farmer model, such as, entity node, aspect node and ILB/OLB. This paper suggests the transformation methodology from the concepts of the Farmer model to the mapping notions of the ISM. Also in reality, TMN agents system which is designed by the Farmer model is transformed to the ISM system design.

We address an access control in the mobile agent-based workflow system. The Role Based Access Control (RBAC) is suitable to model the access control for business processes. However, current RBAC models are not adequate to mobile agent-based workflow system. Because separation of duties becomes complicated and it is impossible to perform several workflows at the same time. To solve these problems, we limit the scope of privilege within the specified task. We define considerations, specification of constraints needed in RBAC when tasks are involved. Also, we present an access control scenario and algorithms in the mobile agent-based workflow system.

This paper suggests the way to perform the handover by predicting the movement route of the mobile terminal by considering the movement pattern of the user. By considering the fact that the most users has the constant movement pattern, the channels needed fur the handover can be reserved, and the required quality of service (QoS) is maintained during handover. The suggested algorithm makes the channel allocation schemes more efficient.