In this paper the performance of communication system in the electrical power line using error correcting codes is analysed. The BCH codes and interleaved code are to be used for correcting burst and random errors in the power line channels. The data rate of 2400 bps and the carrier frequency of 12KHz are assumed. Actual power line noise is recorded and simulated in the BPSK PLC system model.

In this paper, the Automatic Tracking Window(ATW) algorithm is applied to the Generalized Cross-Correlation(GCC) time delay estimation algorithm as a preprocessing. The Linear Prediction(LP) algorithm, which is a pararmetric spectral estimation algorithm, is applied to the time delay estimation. And the ATW, a preprocessing algorithm is applied to this algorithm too. This paper shows that the ATW algorithm attenuates the sidelobes very much and improves the resolution of the timedelay estimation.

A transmission-line discontinuities are analyzed by Finite Element Method. We use quasi-static approxmation to determine the circuit parameters of discontinuities. Delta formulation is introduced so that the cancellation error of potential calculation is reduced. To verify this method, capacitance of coaxial cable with discontinuous and coupling capacitances are calculated by modal expansion. This approach can be used for arbitrary discontinuous conducting patterns of microwave devices.

The optics and the signal processor of dual beam laser Doppler velocimeter(LDV) was fabricated. By using the dual beam and the forward scattering, the optics part of LDV was fabricated. And the signal processor of LDV was designed by the frequency counter type using new 11:6 period timing device in order to remove error signals, and was made of the reference clock of a 500 MHz ECL oscillator. Doppler frequencies from 10KHz to 70MHz can be measured using the signal processor. In the accuracy of the period counting part, from 1.81x10**-4% to 1.27% is estimated, and in the accuracy of the validation logic part, from 0.78% to 14.78% is estimated.

A high performance fully ion-implanted InP JFET was characterized for high speed switching elements. The switch has an insertion loss of 5.5dB with 31.6dB isolation at 1GHz. This device can effectively swithc a byte-multiplexed 2Gb/s signal and an eye-diagram taken at 2Gb/s shows an error-free eye pattern. Therefore, this device can be used as a switching element for high transmission data rate for monolithic integration of optoelectronic circuit in the long-wavelength region.

Formation of TiAs precipitate through the reaction between TiSi2 with C54 structure and heavily doped arsenic ion in poly-silicon, and influence of TiSAs and silicon distribution resulted from the reaction TiSi2+As ->2Si on the morphology degradation have been studied.

Hydrogen plasma-assisted epitaxial(PAE) growth of GaAs/Si and GaAs/Ge/Si with Ge buffer layer has been investigated. By means of photoluminescence, Nomarski microscopu, and $\alpha$-step, it could be known that GaAs on Si with Ge buffer layer has better crystalline quality than GaAs on Si without Ge buffer layer. The stoichiometry of GaAs layer on Si was confirmed by the depth profile of Auger electron spectroscope (AES). Also the native oxide(SiO$_2$) layer on Si substrate was plama-etched and the removal of the oxide layer was confirmed by AES. Photoluminescence peak wavelength of GaAs/Ge/Si with Ge buffer of 1\ulcorner thickness and GaAs growth rate of 160$\AA$/min was 8700$\AA$and FWHM was 12$\AA$.

This paper presents the design and implementation of a performance-driven logic synthesis system that automatically generates circuits satisfying the given timing and fanout constraints in minimal silicon area. After performing technology independent and dependent optimization, the system identifies and resynthesizes the gates with large loading delay due to excessive fanouts to eliminate the critical path. Experimental results for MCNC benchmark circuits show that proposed system generates the circuits with less delay by up to 20%.

This paper presents a graphics accelerator for fast image generation. The accelarator has three major functional blocks: linear interpolator, multipliers and Edgee Painting Tree. Linear interpolator with coupled binary tree structure interpolates functional values of two end points. Two multipliers compute input values of interpolator in parallel. Mask pattern which removes out invalid data is generated by Edge Painting Tree. The proposed architecture in this paper is responsible for 64 pixels and can process about 5,900 10x10polygons per second.