The method of designing microstrip array antenna for low sidelobe level and narrow beam-width using Dolph-Chebyshev array is presented. The widths of microstrip antenna corresponding to excitation coefficients obtained by Dolph-Chebyshev array polynomials is decided by calculating radiation resistance using cavity model analysis. The cascaded array microstrip antenna composed of 10-elements with resonant frequency to be 9.43[GHz] is fabricated by using design method presented in this paper. The experimental results of relatively good characteristics show that its gain, sidelobe level and beam-width are 9[dB], -22[dB] and 8.7[$^{\circ}$].

Diffraction loss occurs when the propagation path is obstructed by mountains and hills between a base station antenna and a moving vehicle antenna in mobile-radio communication. In this paper an approximate mathematical model using Fresnel-Kirchhoff diffraction theory is considered to predict propogation attenuation by natural obstacles with lateral profiles having general shapes. Field tests are conducted using helical and crossed drooping dipole antenna at 820 MHz. The theoretical analysis used in estimating the effects of hills agrees reasonably with experimental data. The results seem to be useful for estimating the level of received power, the minimum allowable input power, the optimum site of base station and consequently, planning terrestrial microwave links.

An optical novelty filter is implemented using photorefractive materal(BaTiO$_{3}$) as a recording materal and commercial liquid crystal TV as a spatial light polarization modulator. If a signal beam incident at the proper, the loop and the crossing angle inside th e crystal is formed to get maximum diffraction efficiency and BaTiO$_{3}$ as a self-pumped phase conjugation mirror show that phase conjugate reflectivity was 20 times as much as ordinary polarization if signal beam is extraordinary. In this paper, the stoke's theorem which is a reciprocal theorem for which is a reciprocal theorem for beam path is experimentally proved, and good output images were obtained with optical experiment of novelty filter which is formed by use of Michelson interferometer.

The cyclic voltammogram characteristics at the magnetized SrO${\cdot}6Fe_{2}O_{3}$ ceramics/(($10^{-3}$M KCI + p-Si powders) and /(($10^{-4}$M CsNO$_3$ + n-GaAs powders) suspension interfaces have been studied using the microelectrophoresis and the cyclic voltammetric method. The negatively charged ions are specifically absorbed on the virgin and the magnetized SrO${\cdot}6Fe_{2}O_{3}$ ceramics surfaces. The zeta potentials of the p-Si and n-GaAs colloidal semiconductors are + 41mV and -44.8mV, respectively. The magnetization effects act as potential barriers at the magnetized SrO${\cdot}6Fe_{2}O_{3}$ interfaces. The positivelely charged p-Si and the negatively charged n-GaAs colloidal semiconductors act as potential barriers at the virgin SrO${\cdot}6Fe_{2}O_{3}$ interfaces. On the other hand, the charged p-Si and n-GaAs colloidal semiconductors act as potential barrier scavengers at the magnetized SrO${\cdot}6Fe_{2}O_{3}$ interfaces. The magnetization effects and the charged colloidal semiconductor effects are irreversible and interdependent.

The electrical properties of ONO interpoly dielectrics grown by polycrystalline silicon have been studied. The polysilicon layer deposited as amorphous state kept its surface smoothness even after subsequent heat cycle induced crystallization. Polysilicon was doped with a POCl$_3$ and arsenic ion implantation. Arsenic was implanted in several different doses. The effective barrier heights calculated from F-N plotting method and breakdown fields increased as the polysilicon doping concentration increased. On the other hand they mere degraded when arsenic concentration in polysilicon exceeded 2{\times}10^{20}[cm^{-3}]$. The reliability of dielectric as monitored by TDDB infant fail and breakdown field showed increasing degradation as doping concentration increased

AlGaAs/GaAs quantum well delta-doped channel FET's have been successfully fabricated using by low-pressure metalorganic chemical vapor deposition(LP-MOCVD). The FET's with a gate dimension of 1.8$\mu$m $\times$ 100$\mu$m have a maximum transconductance of 190 mS/mm and a maximum current density of 425 mA/nm. The devices show extremely broad transconductances with a large voltage swing of 2.4V. The S-parameter measurements have indicated that the current gain and power gain cutoff frequencies of the device were 7 and 15 GHz, respectively. These values are among the best performance reported for GaAs based heterojunction FET's with a similar device geometry.

OEIC(Optoelectronic Integrated Circuit)'s can be integrated horizontally or vertically. Horizontal integration approach is, however, more immune to parasitic and more universally applicable. In this paper, a structural modeling, fabrication and characterization of PIN photodiodes which can be used in the horizontal integration are performed. For device modeling, we build a transmission line model from 2-D device simulation, from which lumped model parameters are extracted. The speed limits of the PIN photodiodes can also be calculated under various structural conditions from the model. Thus optimum design of horizontally integrated PIN photodiodes for high speed operation are possible. Such InGaAs/InP PIN photodiodes for long-wavelength communications are fabricated using pit etch, epi growth, planarization, diffusion and metallization processes. Planarization process using both RIE and wet etching and diffusion process using evaporated Zn$_{3}P_{2}$ film are developed. Characterization of the fabricated devices is performed through C-V and I-V measurements. At a reserve bias of 10V, the dark current is less than 5nA and capacitance is about 0.4pF. The calculated bandwidth using the measured series resistance and capacitance is about 4.23GHz.

Tungsten film was deposited on the TiN surface in a low pressure chemical vapor deposition reactor and chemical reaction mechanism between TiN surface and ($WF_{6}\;and\;SiH_{4}$ was studied. Interaction of ($WF_{6}\;or\;SiH_{4}$ with TiN surface and tungsten was deposited more easily. $WF_6$ reacted with TiN activated the TiN surface to form volatile TiF_4$ and tungsten nuclei were formed. ($SiH_{4}$ was dissociated on the TiN surface to form silicon nuclei. From RBS and AES analysis, we could not detect the impurities(such as Si or TiF$_x$)at the interface between tungsten and TiN. The adhesion at the W/TiN interface became poor when the deposition temperature was below 275$^{\circ}C$.

Photolithography techniques were applied for immobilization of GOD membrane on the pH-ISFET with photo-sensitive polymers to realize ISEFT glucose sensor. This IC technology-compatible glucose sensor showed good sensing characteristics in the wide range of 10-1000 mg/dl glucose concentrations.

This paper presents the design of multi-level logic optimization algorithm and the development of the SMILE system based on the algorithm. Considering the fanin constraints in algorithmic level, SMILE performs global and local optimization in a predefined sequence using heuristic information. Designed under the Sogang Silicon Compiler design environment, SMILE takes the SLIF netlist or Berkeley equation formats obtained from high-level synthesis process, and generates the optimized circuits in the same format. Experimental results show that SMILE produces the promising results for some circuits from MCNC benchmarks, comparable to the popularly used multi-level logic optimization system, MIS.

This paper deals with the scheduling problems, which are the most important subtask in High-level Synthesis. ILP(integer linear programming) formulations are used as a scheduling problem approach.For practical application to digital system design, we have concentrated our attentions on pipelined datapath scheduling. For experiment results, we choose the 5-th order digital wave filter as a benchmark and do the schedule. Finally, we can obtain better and near-optimal scheduling results.

The state machine synthesizer is widely used to FSM synthesis. In this paper, we developed the state machine description language "state CHDL" such as IF, THEN, ELSE, SWITCH, CASE statements. Also, an algorithm for efficient state minimization and two level minimizer of FSM and graphical user interface-pin map window, supporting the designer with input-ouput effency, are presented.

In this paper, a new heuristic algorithm for designing combinational circuits suitable for verification testing is presented. The design method consists of argument reduction, input partitioning, output partitioning, and logic minimization. A new heuristic algorithm for input partitioning and output partitioning is developed and applied to designing combinational circuits to demonstrate its effectiveness.