A narrow-band dual TE$_{111}$ mode circular waveguide filter for Ku-Band satellite transponder was designed and manufactured based on a new model of the filter. We calculated the cavity size, pin polarizer depth and diameter, iris length and width, and used Bethe's Small Diffraction Theory and Chon's Correction Formular in order to obtain exact Result for each cavity. The designed dual model waveguide filter was manufactured with invar in order to maintain the thermal stability, and the filter performance was improved through the thermal test and vibration test to endure in the cosmic environment.

Because of their high sensitivity and moderate bandwidth, superconducting receivers with SIS (Superconductor Insulator Superconductor) tunnel junction mixer are now widely used for millimeter wave radio astronomy. In this paper we have introduced how to determine the parameters of SIS tunnel junction which have to be optimized to achieve a good mixer performance. From these results of optimized junction parameters determined by this methods, SIS junctions which consist of a series array of four Nb/Al-AlOx/Nb junctions with each area 3.4${\mu}m^{2}$ have been fabricated by SNEP (Selective Niobium Etching Process) and RIE (Reactive Ion Eching). Also we have tested their DC current-voltage characteristics. These SIS junctions will be used as a mixer for 100GHz band cosmic waves receiver.

The base-collector capacitance of an npn bipolar transistor in bipolar or BiCMOS technology has significant influence on the switching performances, and comprises pnjunction component and MOS component. Both components have complicated dependences on the isolation oxide structure, epitaxial doping density, and bias voltage. Analytical/empirical formulas for both components are derived in this paper for a generic isolation structure as a function of epitaxial doping density and bias voltage based on some theoretical understanding and two-dimensional device simulations. These formulas are useful in estimating the effect of device isoation schemes on the switching speed of bipolar transistors.

Separate-confinement hetero-structure (SCH) broad area Laser Diodes (LD's) were fabricated from $Al_{0.07}$Ga$_{0.93}$/. As single-quantum-well (SQW) grown by metal organic chemical vapor deposition (MOCVD). Under pulsed operation, we obtained maximum output powers of about 0.8watt/facet and 1.83watt/facet from LD's with 60$\mu$m and 160$\mu$m channel width, respectively, without facet coatings. The differential quantum efficiency of the 60$\mu$m wide LD was about 21.7%/facet and its threshold current density was about 1k [A/cm$^{2}$]. The differential quantum efficiency of the 160$\mu$m wide LD was about 25.6%/facet and its threshold current density was about 1k[A/cm$^{2}$]. The minimum threshold current density of 60$\mu$m wide LD's was 620[A/cm$^{2}$] when the cavity length was 603$\mu$m and the minimum threshold current density of 160$\mu$m wide Ld's was 675[A/cm$^{2}$] when the cavity length was 752$\mu$m. The internal quantum efficienty and the internal loss of both LD's were 92.3% and 18.1cm$^{1}$, respectively.

A reflection type 16x8 S-SEED array from LP(Low Pressure)-MODVD-grown GaAs/AlGaAs extremely shallow quantum well(ESQW) structures, with 4% Al fraction, has been fabricated. Its intrinsic region consists of 50 pairs of alternating 100.angs. GaAs and 100.angs. $Al_{0.04}$Ga$_{0.96}$As layers. A multilayer reflector stack of $Al_{0.04}$/Ga$_{0.96}$ As(599$\AA$)/AlAs(723$\AA$) was incorporated for the reflection plane below the p-i-n structures. The device processing after the MOCVD growth includes the mesa etching, isolation etching, insulator deposition, p & n metallization, and AR(Anti-Reflection) coating. For switching characteristics of the S-SEED in the form of p-i-n ESQW diode, the maximum optical negative resistance was observed at 856nm. Reflectance measurements showed a change from 15.6% to 43.3% for +0.9V to -6V bias. The maximum contrast ration of the S-SEED array was 2.0 and all the 128 devices showed optical bistability with contrast ratios over 2.4 at 5V reverse bias.

This paper describes the fabrication process and electrical characteristics of PSA (Polysilicon Self-Align) bipolar transistors with a thin base width of 1100.angs.. To realize this shallow junction depth, one-step rapid thermal annealing(RTA) technology has been applied instead of conventional furnace annealing process. It has been shown that the series resistances and parasitic capacitances are significantly reduced in the device with emitter area of 1${\times}4{\mu}m^{2}$. The switching speed of 2.4ns/gate was obtained by measuring the minimum propagation delay time in the I$^{2}$L ring oscillator with 31 stages.

N-channel TFTs fabricated on the pre-amorphized (by Si ion implantation) and recrystallized Si film having 10.1V threshold voltage, 20.7cm$^{2}$/V$\cdot$s field effect mobility and ~10$^{5}$/ ON/OFF ratio, whowed improved characteristics comparing to those obtained from the as-deposited (by LPCVD) poly Si film which had 11.2V, 9cm$^{2}$/V$\cdot$s and ~10$^{4}$ respectively.

PZT thin film deposited by rf magnetron sputtering was annealed by rapid thermal process(RTP) in PbO ambient to prevent vaporing of Pb and interface reactions. Si and TiN/Ti/Si substrates were prepared to survey application of TiN/Ti layer which can prevent interface interaction with Si and crack of PZT thin films. As temperature increased. PZT thin films surface on Si substrate appeared more severe cracks which should affect electrical properties deadly. TiN/Ti(40-150${\mu}{\Omega}{\cdot}cm$) layer applied for buffer layer suppressed interface interaction and film cracking. The measured leakage current(LC) and breakdown voltage(BV) of PZT thin film on TiN/Ti/Si substrate annealed at 650$^{\circ}$C for 15 sec (thickness of 2500$\AA$) were 38 nA/cm2 and 3.5 MV/cm and dielectric constant was 310 at 1 MHz, and remanent polarization (Pr) and coercive field (Ec) were 6.4${\mu}C/cm^{2}$ and 0.2MV/cm at 60 Hz, respectively.

This paper presents the design and implementation of SVSIM (Sogang VHDL SIMulator), a multi-level VHDL simulator, designed for the construction of an integrated VGDL design environment. The internal model of SVSIM is the hierarchical C/DFG which is extended from C/DFG to include the network hierarchy and local/glabal control informations. Hierarchical network is not flattened for simulation, resulting in the reduction of space complexity. The predufined/user-defined types except for the record type and the predefined/user-defined attributes are supported in SVSIM. Algorithmic-level descriptions can be siumlated by the support of recursive procedure/function calls. Input stimuli can be generated by command script in stimuli file or in VHDL source code. Experimential results show SVSIM can be efficiently used for the simulation of the pure behavioral descriptions, structural descriptions or mixture of these.