The surge impedance of grounding systems must be accurately computed for a safe grounding design. Specifically, the case of radio relay station in a mountaintop region is required special design method using transient analyses. To approach these design objectives, this paper presents an algorithm to compute the surge impedance of two or more grounding systems using the Laplace Transform technique and deals with the analysis of the transient characteristics on grounding systems. Also, simulation results are compared with the measured data to prove the validity of the algorithm.

In is well-known that system performance in the high speed digital radio communication system is usually deteriorted due to the frequency selective fading distortion. In this paper, bit error rate(BER) performance by the reception phase error in cellular mobile communication systems is derived and analyzed. The system is modeled as a frequency selective fast Rayleigh fading channel corrupted by additive white gaussian noise(AWGN) and co-channel interference(CCI). Our numerical results show that for the 24KBaud(48Kb/s) $\pi$/4-DQPSK operated at carrier frequency 800 MHz and C/I<20 dB, the BER will be dominated by CCI if the vehicular speed is below 100 Km/h. The results show that performance, when reception phase error is below $\pi$/12, is deterioreted less than 3 dB, and that performance, when reception phase error is above $\pi$/12, is degraded over 3 dB.

In this paper, we present analysis results of various intermodulation products (IMPs) evaluation methods previously proposed for nonlinear systems. The results indicate that out of these methods, Fuenzalida and Simbo's method is the best for efficient evaluation of IMPs. Also, we present a detailed mathematical analysis of IMP and show how to apply the equations related to IMP to actual program implementations with examples. In this paper, we newly introduce three methods to reduce the IMP calculation time and improve the accuracy of the outputs :1) TWTA curve fitting method by LS (Least Square), 2) IMP evaluation technique which is based on a look-up table 3) Gaussian spectral shaping for PSK signal instead of convolution. The IMP evaluation results obtained by the new approaches introduced in this paper resulted in a good match with the published outputs in the open literature and showed improved performance especially in the TWTA curve .

The 607 nm GaInP/AlInP distributed bragg reflector (DBR) lasers using the second order gratings period of 184.7 nm were fabricated by gas source molecular beam epitaxy (GSMBE) and the conventional holographic method. GaInP/AlInP DBR lasers show single mode operations up to 1.8 times the threshold currents with a wavelength of 607 nm at 140 K and a wavelength shift of 0.033 nm/K is observed. No mode hopping was found in the temperature ranging from 120 to 165K.

In this paper, we present a simple and general lifetime prediction model for PMOSFET by using the correlation between transconductance degradation and gate current influence to solve a problem that that I$_{b}$ is dependent on drain structure. The suggested model is applied to a different channel, drain structured PMOSFET. For all PMOSFETs, dg$_{m}$/g$_{m}$ of PMOSFET appears with one straight line about Q$_{g}$, therefore, this model using I$_{g}$ is consistent with experiment result independently of channel, drain structure. It is, therefore, proposed that a model using I$_{g}$ has a general applicability for PMOSFET's.

In this study, the degradation characteristics of drain output resis-tance was described due to hot electron effects. An semi-empirical model for the degraded drain output resistance was derived from the measured device characteristics. The suggested model was verified from the measured data and the device parameter dependence was also analyzed. The degradation of drain output resistance was increased with stress time and had linear relationship with the degradation of drain current. The device lifetime which was defined by failure criteria of drain output resistance (such as $\Delta$ro/roo=5%) was equivalent to that of failure criteria of drain current (such as $\Delta$ID/ID=5%)

Owing to the nature of locality in mask layouts, it appears that most mask layout problems can be solved by transforming a part of the given mask layout into a better layout segment continuously toward a global suboptimal solution. This notion of local transformation addresses major weak points of existing mask layout processing systems, which lack both extensibility and unifiability. This paper attempts to elaborate upon developing a new rule-based mask layout transformation system wherein most of the mask layout problems can be solved under the unified framework of local mask layout transformation. The rule-based mask layout transformation system is applicable to various mask layout problems such as net extraction, mask layout compaction, mask layout editing, and design rule checking. The experimental results show that the rule-based expert system approach is an efficient means of solving those mask layout problems, and thus confronting major drawbacks of existing layout processing systems.

An efficient test method based on march test is presented to cover line leakage failures associated with bit and word lines or mega bit DRAM chips. A modified column march (Y-march) pattern is derived to improve fault coverage against the data retention failure. Time delay concept is introduced to develop a new column march test algorithm detecting various data retention failures. A built-in test circuit based on the column march pattern is designed and verified using logic simulation, confirming correct test operations.

This paper proposes a new test pattern generation methodology for combinational logic circuits using neural networks based on a modular structure. The CUT (Circuit Under Test) is described in our gate level hardware description language. By conferring neural database, the CUT is compiled to an ATPG (Automatic Test Pattern Generation) neural network. Each logic gate in CUT is represented as a discrete Hopfield network. Such a neual network is called a gate module in this paper. All the gate modules for a CUT form an ATPG neural network by connecting each module through message passing paths by which the states of modules are transferred to their adjacent modules. A fault is injected by setting the activation values of some neurons at given values and by invalidating connections between some gate modules. A test pattern for an injected fault is obtained when all gate modules in the ATPG neural network are stabilized through evolution and mutual interactions. The proposed methodology is efficient for test generation, known to be NP-complete, through its massive paralelism. Some results on combinational logic circuits confirm the feasibility of the proposed methodology.